lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 27

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

LOGIC Devices Incorporated
Figure 13 - Write Pointer ‘Clear’ and ‘Set’ Timing
Figure 14 - Read Pointer ‘Clear’ Timing
Figure 15 - Read Pointer Full-Time Override using 24bit External Address
ADDR
Qx[11:0]
*
*
RCLK
RSET
D[11:0]
WCLR
WCLK
WSET
WEN = LOW
CLR and SET both programmed to be falling edge sensitive
Rising Edge 4: Sets Write Pointer to Address A (based on WADDR) and latches data on D to be written in Address A
Q[11:0]
23-0
Rising Edge 1: Clears Write Pointer and latches data on D to be written in address 0
RCLK
REN = LOW
NOTE: CLR programmed as being falling edge sensitive
It takes 9 REN-enabled rising edges of RCLK (including the edge that latches a LOW on CLR) to pass the contents of address 0 to the Q port.
CLR
NOTE: RSET programmed to be active LOW (full-time read address override)
OE = LOW
NOTE: It takes 14 rising edges of RCLK upon setting/jumping the Read pointer
(to the 24bit Address "A0" on ADDR) for the contents of location A0 to be dumped onto Q
(n)
t
D
RENx = LOW
(n–2)
www.logicdevices.com
t
(n) ) n
(
( n)
RWS
(n+1)
1
RDWR = HIGH
t
RWH
t
D
(n-1) ) 1
(
( n-1)
- n
(n+1)
t
t
DS
RWS
t
DS
(0)
t
1
2
DH
1
t
DH
MODE=x0xx
(n)
(n+2) ) 2
n (
( n+2)
+
(1)
27
2
13
(2)
8
3
PRELIMINARY
t
RWH
(n+13)
(n+8) ) 8
n (
( n+8)
+
t
RWS
High Performance Memory Product
3
14
9
(A)
4
t
D
(A
Video Memory / FIFO
(0)
0
)
10
(A+1)
5
MEMORY
FRAME
January 23, 2008 LDS-44xx-A
(1) ) 1
(
( 1)
(A
1
)
LF4460
LF4430
LF4415