km416s8030 Samsung Semiconductor, Inc., km416s8030 Datasheet - Page 5

• Manufacturer Part Number: km416s8030
• Description: 2m X 16bit X 4 Banks Synchronous Dram
• Manufacturer: Samsung Semiconductor, Inc.

KM416S8030
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
Note :
(AC operating conditions unless otherwise noted)
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid
output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
and then rounding off to the next higher integer.
(Fig. 1) DC Output Load Circuit
870
Parameter
Parameter
CAS latency=3
CAS latency=2
3.3V
1200
50pF
V
V
Symbol
t
t
t
t
t
t
t
t
t
t
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC(min)
RDL(min)
CDL(min)
BDL(min)
CCD(min)
OH
OL
(DC) = 0.4V, I
(VDD = 3.3V
(DC) = 2.4V, I
16
20
20
48
68
-8
8
OL
OH
0.3V, T
= 2mA
= -2mA
A
= 0 to 70 C)
tr / tf = 1 / 1
See Fig. 2
-H
20
20
20
50
70
10
2.4 / 0.4
Value
1.4
1.4
Version
Output
100
1
1
1
2
1
20
20
20
50
70
10
-L
(Fig. 2) AC Output Load Circuit
Z0=50
-10
20
24
24
50
80
12
Preliminary
CMOS SDRAM
REV. 2 Mar. '98
Unit
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
ns
Vtt=1.4V
Unit
50
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4