km416v4000b Samsung Semiconductor, Inc., km416v4000b Datasheet - Page 8

• Manufacturer Part Number: km416v4000b
• Description: 4m X 16bit Cmos Dynamic Ram With Fast Page Mode
• Manufacturer: Samsung Semiconductor, Inc.

KM416V4000B, KM416V4100B
NOTES
KM416V40(1)00B Truth Table
10.
11.
12.
RAS
5.
6.
7.
8.
9.
1.
2.
3.
4.
H
L
L
L
L
L
L
L
L
An initial pause of 200
before proper device operation is achieved.
V
V
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
If
Assumes that
t
or V
t
acteristics only. If
duration of the cycle. If
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles.
Operation within the
If
These specifications are applied in the test mode.
In test mode read cycle, the value of
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
OFF
WCS
IH
IH
t
t
RCD
RAD
(min) and V
(min) and V
ol
(min)and
,
.
t
t
RWD
is greater than the specified
is greater than the specified
RCH
LCAS
,
or
X
H
H
H
L
L
L
L
L
t
CWD
t
t
t
OEZ
RRH
IL
RCD
IL
(max) and are assumed to be 5ns for all inputs.
(max) are reference levels for measuring timing of input signals. Transition times are measured between
and
(max) define the time at which the output achieves the open circuit condition and are not referenced V
t
WCS
must be satisfied for a read cycle.
t
t
RCD
t
RCD
RAD
t
§ Á
AWD
UCAS
t
t
(max).
CWD
WCS
(max) limit insures that
(max) limit insures that
is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
X
H
H
H
L
L
L
L
L
are non restrictive operating parameters. They are included in the data sheet as electrical char-
(min), the cycle is an early write cycle and the data output will remain high impedance for the
t
CWD
(min),
t
t
RAD
RCD
t
RAC
(max) limit, then access time is controlled by
(max) limit, then access time is controlled exclusively by
W
X
X
H
H
H
H
L
L
L
t
RWD
,
t
AA
,
t
t
t
RWD
t
RAC
RAC
CAC
(min) and
(max) can be met.
(max) can be met,
is delayed by 2ns to 5ns for the specified values. These parameters
OE
X
X
H
H
H
H
L
L
L
t
AWD
DQ0 - DQ7
DQ-OUT
DQ-OUT
t
DQ-IN
DQ-IN
AWD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
t
RCD
RAD
-
(min), then the cycle is a read-modify-write cycle
(max) is specified as a reference point only.
(max) is specified as a reference point only.
t
AA
.
DQ8-DQ15
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
t
CAC
CMOS DRAM
.
Word Read
Word Write
Byte Read
Byte Read
Byte Write
Byte Write
Standby
Refresh
STATE
-
oh