km416v4104c Samsung Semiconductor, Inc., km416v4104c Datasheet

km416v4104c

Manufacturer Part Number

km416v4104c

Description

4m X 16bit Cmos Dynamic Ram With Extended Data Out

Manufacturer

Samsung Semiconductor, Inc.

Datasheet

1.KM416V4104C.pdf (36 pages)

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Download datasheet (539Kb)

KM416V4004C,KM416V4104C

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random

access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal

or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh

capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Sam-

sung s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Part Identification

• Active Power Dissipation

• Refresh Cycles

* Access mode & RAS only refresh mode

• Performance Range

KM416V4004C*

KM416V4104C

Speed

CAS-before-RAS & Hidden refresh mode

- KM416V4004C/C-L(3.3V, 8K Ref.)

- KM416V4104C/C-L(3.3V, 4K Ref.)

: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

-45

-5

-6

Speed

-45

Part

-5

-6

NO.

45ns

50ns

60ns

RAC

Refresh

cycle

12ns

15ns

17ns

4M x 16bit CMOS Dynamic RAM with Extended Data Out

324

288

252

CAC

Normal

64ms

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

104ns

74ns

84ns

Refresh time

Unit : mW

468

432

396

128ms

L-ver

17ns

20ns

25ns

HPC

DESCRIPTION

(A0~A11)*1

(A0~A9)*1

UCAS

LCAS

A0~A12

RAS

A0~A8

FUNCTIONAL BLOCK DIAGRAM

• Extended Data Out Mode operation

• 2 CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• Self-refresh capability (L-ver only)

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) packages

• +3.3V 0.3V power supply

Note) *1 : 4K Refresh

Control

Clocks

Row Address Buffer

Col. Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

VBB Generator

Column Decoder

4,194,304 x 16

Memory Array

Row Decoder

Cells

CMOS DRAM

Vcc

Vss

Data out

Data in

Lower

Buffer

Lower

Buffer

Upper

Buffer

DQ15

DQ0

DQ7

DQ8

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