km416v4104c Samsung Semiconductor, Inc., km416v4104c Datasheet - Page 9
km416v4104c
Manufacturer Part Number
km416v4104c
Description
4m X 16bit Cmos Dynamic Ram With Extended Data Out
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.KM416V4104C.pdf
(36 pages)
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KM416V4004C,KM416V4104C
16.
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24.
t
t
t
t
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
t
If
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.
CWL
CSR
CHR
DS
ASC
t
RASS
DQ0 ~ DQ15
is specified for the earlier CAS falling edge and
is referenced to earlier CAS falling before RAS transition low.
is referenced to the later CAS rising high after RAS transition low.
is specified from W falling edge to the earlier CAS rising edge.
6ns, Assume t
100us, then RAS precharge time must use
UCAS
UCAS
LCAS
LCAS
RAS
T
=2.0ns, if t
ASC
t
6ns, then t
DS
Din
t
CSR
HPC
t
DH
(min) and t
t
t
DH
RPS
is specified by the later CAS falling edge in early write cycle.
instead of
t
CHR
CAS
(min) must be increased by the value of "6ns-t
t
RP
.
CMOS DRAM
ASC
".