tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet - Page 33

• Manufacturer Part Number: tc59lm913amb-50
• Description: 512mbits Network Fcram1 Sstl_2 Interface
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Command
BA0~BA2
L/UDQS
A13~A0
MODE REGISTER SET TIMING (CL = 4, BL = 4)
(input)
(input)
From Write operation to Mode Register Set operation.
CLK
CLK
DQ
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
WRA
UA
BA
0
LAL
LA
1
2
WL+BL/2
3
DESL
D0 D1 D2 D3
4
5
RDA
6
(opcode)
BA0="0"
BA1="0"
BA2="0"
MRS
Valid
7
8
9
10
DESL
I
RSC
11
TC59LM913AMB-50
12
2005-11-08 33/46
13
WRA
RDA
UA
BA
14
or
Rev 1.1
LAL
LA
15