tc59lm913amb-50 TOSHIBA Semiconductor CORPORATION, tc59lm913amb-50 Datasheet - Page 38

• Manufacturer Part Number: tc59lm913amb-50
• Description: 512mbits Network Fcram1 Sstl_2 Interface
• Manufacturer: TOSHIBA Semiconductor CORPORATION

FUNCTIONAL DESCRIPTION
Network FCRAM
perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
FCRAM
CLOCK INPUTS: CLK &
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The L/UDQS and DQ output are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN:
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL:
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0~BA2
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
ADDRESS INPUTS: A0~A13
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
The CS and FN inputs are a control signal for forming the operation commands on FCRAM
The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Also, when BA2 input assign to A14 input, TC59LM913AMB can function as 4bank devices.
TM
is an acronym of Fast Cycle Random Access Memory. The Network FCRAM
TM
PD
8 bank operation
4 bank operation
Bank #0
Bank #1
Bank #2
Bank #3
Bank #4
Bank #5
Bank #6
Bank #7
CLK
BA0
UPPER ADDRESS
A0~A13, BA2(A14)
0
1
0
1
0
1
0
1
A0~A13
CS
& FN
BA1
0
0
1
1
0
0
1
1
LOWER ADDRESS
A0~A7
A0~A7
BA2
TC59LM913AMB-50
0
0
0
0
1
1
1
1
2005-11-08 38/46
TM
is competent to
Rev 1.1
TM
. Each