73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet
73s1217f68im
Related parts for 73s1217f68im
73s1217f68im Summary of contents
Page 1
Simplifying System Integration™ GENERAL DESCRIPTION The Teridian Semiconductor Corporation 73S1217F is a versatile and economical CMOS System-on-Chip device intended for smart card reader applications. The circuit features an ISO-7816 / EMV interface, an USB 2.0 interface (full-speed 12Mbps - slave) ...
Page 2
FEATURES 80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 64kB Flash memory (lockable) • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer Oscillators: • Single low-cost ...
Page 3
Hardware Description ......................................................................................................................... 8 1.1 Pin Description .............................................................................................................................. 8 1.2 Hardware Overview .................................................................................................................... 11 1.3 80515 MPU Core ........................................................................................................................ 11 1.3.1 80515 Overview ............................................................................................................. 11 1.3.2 Memory Organization .................................................................................................... 11 1.4 Program Security ...
Page 4
Figures Figure 1: IC Functional Block Diagram ......................................................................................................... 7 Figure 2: Memory Map ................................................................................................................................ 15 Figure 3: Clock Generation and Control Circuits ........................................................................................ 23 Figure 4: Oscillator Circuit ........................................................................................................................... 25 Figure 5: Detailed Power Management Logic Block Diagram .................................................................... 26 ...
Page 5
Tables Table 1: 73S1217 Pinout Description ........................................................................................................... 8 Table 2: MPU Data Memory Map ............................................................................................................... 11 Table 3: Flash Special Function Registers ................................................................................................. 13 Table 4: Internal Data Memory Map ........................................................................................................... 14 Table 5: Program Security Registers .......................................................................................................... 17 Table ...
Page 6
Table 58: The INT5Ctl Register .................................................................................................................. 56 Table 59: The ACOMP Register ................................................................................................................. 57 Table 60: The INT6Ctl Register .................................................................................................................. 58 Table 61: The LEDCtl Register ................................................................................................................... 59 Table 62: The DAR Register ....................................................................................................................... 63 Table 63: The WDR Register ...
Page 7
VDD PLL and TIMEBASES X12IN 12MHz OSCILLATOR X12OUT X32IN 32kHz OSCILLATOR X32OUT RTC VDD USB I/O D+ and D- LOGIC GND ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 KEYPAD INTERFACE COL0 COL1 COL2 COL3 COL4 USR0 USR1 USR2 USR3 USR4 USR5 ...
Page 8
Hardware Description 1.1 Pin Description Pin Name X12IN 10 I Figure 29 X12OUT 11 O Figure 29 X32IN 8 I Figure 30 X32OUT 7 O Figure Figure Figure 45 ROW(5:0) 0 ...
Page 9
Pin Name INT3 48 I Figure 35 INT2 49 I Figure 35 SIO 47 IO Figure 31 SCLK 45 O Figure 32 PRES 53 I Figure 44 CLK 55 O Figure 42 RST 57 O Figure ...
Page 10
Pin Name OFF_REQ 52 O Figure 36 TBUS(3:0 RXTX 43 IO ERST 38 IO ISBR 3 IO TCLK 39 I ANA_IN 15 AI Figure 41 LED0 4 IO Figure 39 SEC 2 ...
Page 11
Hardware Overview The 73S1217F single smart card controller integrates all primary functional blocks required to implement a smart card reader with host serial and / or USB interface. Included on chip are an 8051-compatible microprocessor (MPU) which executes up ...
Page 12
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from location ...
Page 13
Table 3: Flash Special Function Registers Register SFR R/W Address ERASE 0x94 W PGADDR 0xB7 R/W FLSHCTL 0xB2 R/W W R/W Internal Data Memory: The internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data ...
Page 14
Addres Direct Addressing s 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in ...
Page 15
Address Use Address 0xFFFF 0xFFFF 0XFF80 0xFF7F 0XFE00 0xFDFF 0XFC00 0xFBFF 0x0800 0x07FF Flash Program Memory 64K Bytes 0x0000 0x0000 Program Memory External Data Memory Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard ...
Page 16
Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE ...
Page 17
Register SFR R/W Address FLSHCTL 0xB2 R/W W R/W TRIMPCtl 0xFFD1 W FUSECtl 0xFFD2 W SECReg 0xFFD7 W R R/W R/W Rev. 1.2 Table 5: Program Security Registers Description Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer ...
Page 18
Special Function Registers (SFRs) The 1217 utilizes numerous SFRs to communicate with the many 1217 peripherals. This results in the need for more SFR locations outside the direct address IRAM space (0x80 to 0xFF). While some peripherals are mapped ...
Page 19
IRAM Special Function Registers (Generic 80515 SFRs) Table 7 shows the location of the SFRs and the value they assume at reset or power-up. Table 7: IRAM Special Function Registers Reset Values Name Location Reset Value SP 0x81 0x07 ...
Page 20
Name Location Reset Value KROW 0XD2 0x3F KSCAN 0XD3 0x00 KSTAT 0XD4 0x00 KSIZE 0XD5 0x00 KORDERL 0XD6 0x00 KORDERH 0XD7 0x00 BRCON 0xD8 0x00 A 0xE0 0x00 B 0xF0 0x00 1.5.3 External Data Special Function Registers (SFRs) A map ...
Page 21
Name Location Reset Value FUSECtl 0x FFD2 0x00 VDDFCtl 0x FFD4 0x00 SECReg 0x FFD7 0x00 MISCtl0 0x FFF1 0x00 MISCtl1 0x FFF2 0x10 LEDCtl 0x FFF3 0xFF Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the ...
Page 22
Program Status Word (PSW): MSB CV AC Bit Symbol PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of ...
Page 23
Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 73S12xxF Software User’s Guide. and of the associated op-codes is contained in ...
Page 24
The master clock control register enables different sections of the clock circuitry and specifies the value of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper operation of some of the peripheral blocks ...
Page 25
MPU Clock Control Register (MPUCKCtl): 0xFFA1 MSB – – Bit Symbol MPUCKCtl.7 – MPUCKCtl.6 – MPUCKCtl.5 MDIV.5 This value determines the ratio of the MPU master clock frequency to MPUCKCtl.4 MDIV.4 the VCO frequency (MCLK) such that MPUCKCtl.3 MDIV.3 MPUClk ...
Page 26
Power Supply Management The detailed power supply management logic block diagram is shown in Figure 5. V BUS V BUSTH V BAT ON_OFF Debounce Circuit INT MPU PWRDN* *PWRDN bit in MISCtl0 Figure 5: Detailed Power Management Logic Block ...
Page 27
V is typically supplied by an external power supply and ranges in value from 4.4 to 5.5 volts (6.5V BUS maximum expected to be supplied from a battery of three to four series connected cells with a voltage ...
Page 28
SCPWRDN bit in the Smart Card V (VccCtl) high after it has completed all shutdown activities. When SCPWRDN is set high, the circuit will deactivate the smart card interface if required and turn off ...
Page 29
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram. MISCtl0 ...
Page 30
USR0 USR1 USR[7:0] Control USR2 USR3 USR4 USRxINTSrc set to 4(ext INT0 high) USR5 or USR6 6(ext INT0 low) USR7 INT4 INT5 RESETB Notes: 1. The counters are clocked by the MPUCLK Terminal count (high at overflow) ...
Page 31
External Interrupt Control Register (INT5Ctl): 0xFF94 MSB PDMUX – RTCIEN RTCINT USBIEN Bit Symbol When set = 1, enables interrupts from USB, RTC, Keypad (normally going to int5), Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to ...
Page 32
Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 MSB – – Bit Symbol MISCtl1.7 – MISCtl1.6 – Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is passed through with no change. When FRPEN = 0 a one-shot ...
Page 33
Master Clock Control Register (MCLKCtl): 0x8F MSB HSOEN KBEN Bit Symbol High-speed oscillator enable. When set = 1, disables the high-speed crystal oscillator and VCO/PLL system. This bit is not changed when the MCLKCtl.7 HSOEN PWRDN bit is set but ...
Page 34
Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is setup via this register. MSB SMOD – Bit Symbol PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – ...
Page 35
Interrupts The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually ...
Page 36
Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 32. Once the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt service is ...
Page 37
Interrupt Enable 1 Register (IEN1): 0xB8 MSB – SWDT Bit Symbol IEN1.7 – IEN1.6 SWDT Not used for interrupt control. IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. ...
Page 38
Timer/Counter Control Register (TCON): 0x88 MSB TF1 TR1 Bit Symbol TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 ...
Page 39
Interrupt Request Register (IRCON): 0xC0 MSB – – Bit Symbol IRCON.7 – IRCON.6 – IRCON.5 IEX6 External interrupt 6 flag. IRCON.4 IEX5 External interrupt 5 flag. IRCON.3 IEX4 External interrupt 4 flag. IRCON.2 IEX3 External interrupt 3 flag. IRCON.1 IEX2 ...
Page 40
Table 26: Control Bits for External Interrupts Enable Bit Description EX0 Enable external interrupt 0 EX1 Enable external interrupt 1 EX2 Enable external interrupt 2 EX3 Enable external interrupt 3 EX4 Enable external interrupt 4 EX5 Enable external interrupt 5 ...
Page 41
Interrupt Priority 1 Register (IP1): 0xB9 MSB – – 1.7.5.6 Interrupt Sources and Vectors Table 32 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag Description N/A IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 ...
Page 42
UART The 80515 core of the 73S1217F includes two separate UARTs that can be programmed to communicate with a host. The 73S1217F can only connect one UART at a time since there is only one set of TX and ...
Page 43
Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is set up via this register. MSB SMOD – Bit Symbol PCON.7 SMOD PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 PCON.2 GF0 PCON.1 STOP ...
Page 44
Miscellaneous Control Register 0 (MISCtl0): 0xFFF1 Transmit and receive (TX and RX) pin selection and loop back test configuration are set up via this register. MSB PWRDN – Bit Symbol MISCtl0.7 PWRDN MISCtl0.6 – MISCtl0.5 – MISCtl0.4 – MISCtl0.3 – ...
Page 45
Transmit and receive data are transferred via this register. MSB SM0 SM1 Bit Symbol S0CON.7 SM0 Mode S0CON.6 SM1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 ...
Page 46
Serial Interface Control Register (S1CON): 0x9B The function of the serial port depends on the setting of the Serial Port Control Register S1CON. MSB SM – Bit Symbol S1CON.7 SM S1CON.6 – S1CON.5 SM21 S1CON.4 REN1 S1CON.3 TB81 S1CON.2 RB81 ...
Page 47
Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, meaning that it counts ...
Page 48
Table 41: Timers/Counters Mode Description M1 M0 Mode 0 0 Mode Mode Mode Mode 3 Mode 0 Putting either timer/counter into mode 0 configures 8-bit timer/counter with a ...
Page 49
Timer/Counter Control Register (TCON): 0x88 MSB TF1 TR1 Bit Symbol The Timer 1 overflow flag is set by hardware when Timer 1 overflows. TCON.7 TF1 This flag can be cleared by software and is automatically cleared when an interrupt is ...
Page 50
Interrupt Enable 0 Register (IEN0): 0xA8 MSB EAL WDT Bit Symbol IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before ...
Page 51
Interrupt Priority 0 Register (IP0): 0xA9 MSB – WDTS Bit Symbol IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The internal reset will be generated, but this bit will not be cleared by the reset. ...
Page 52
User (USR) Ports The 73S1217F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the ...
Page 53
External Interrupt Control Register (USRIntCtl1) : 0xFF90 MSB – U1IS.6 External Interrupt Control Register (USRIntCtl2) : 0xFF91 MSB – U3IS.6 External Interrupt Control Register (USRIntCtl3) : 0xFF92 MSB – U5IS.6 External Interrupt Control Register (USRIntCtl4) : 0xFF93 MSB – U7IS.6 ...
Page 54
Real-Time Clock with Hardware Watchdog (RTC) Figure 10 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator signal and divider logic to produce 0.5-second time marks. The time marks are used to ...
Page 55
A 32-bit RTC counter is clocked by a selectable clock (1/ second) to measure time. A trimming function is provided such that a trim value is accumulated in a 24-bit accumulator at the same rate as the RTC ...
Page 56
There are 3 sets of registers to load the RTC 24-bit accumulator, 32-bit counter and 23-bit trim registers. The registers are loaded when the RTCLD bit is set in RTCCtl. Register RTCCnt3 RTCCnt[31:24] Register Table 57: The 24-bit RTC Trim ...
Page 57
Analog Voltage Comparator The 73S1217F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The ...
Page 58
External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. 2 INT6Ctl.3 I2CIEN I C interrupt enabled. 2 INT6Ctl.2 I2CINT I C interrupt ...
Page 59
LED Driver The 73S1217F provides a single dedicated output pin for driving an LED. The LED driver pin can be configured as a current source that will pull to ground to drive an LED that is connected to VDD ...
Page 60
I C Master Interface The 73S1217F includes a dedicated fast mode, 400kHz I or write bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers: • Device ...
Page 61
Figure 11 shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2C_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2C_Interrupt SDA Device Address MSB SCL START condition ...
Page 62
The following diagram shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START ...
Page 63
Device Address Register (DAR): 0xFF80 MSB DVADR.6 DVADR.5 DVADR.4 DVADR.3 DVADR.2 Bit Symbol DAR.7 DAR.6 DAR.5 DVADR DAR.4 Slave device address. [0:6] DAR.3 DAR.2 DAR.1 DAR.0 I2CRW If set = 0, the transaction is a write operation. If set = ...
Page 64
I2C Secondary Write Data Register (SWDR): 0XFF82 MSB SWDR.7 SWDR.6 SWDR.5 Bit SWDR.7 SWDR.6 SWDR.5 SWDR.4 Second Data byte to be written to the I and Status register (CSR) is set = 1. SWDR.3 SWDR.2 SWDR.1 SWDR.0 I2C Read Data ...
Page 65
I2C Secondary Read Data Register (SRDR): 0XFF84 MSB SRDR.7 SRDR.6 SRDR.5 Bit SRDR.7 SRDR.6 SRDR.5 SRDR.4 Second Data byte to be read from the I and Status register (CSR) is set = 1. SRDR.3 SRDR.2 SRDR.1 SRDR.0 I2C Control and ...
Page 66
External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I When set =1, the I ...
Page 67
Keypad Interface The 73S1217F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 13 shows a simplified block diagram of the keypad interface. Keypad Clock Column Value 5 ...
Page 68
KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When a valid key is detected, an interrupt is generated and ...
Page 69
KORDERL / H Registers: Column Scan Order More than 1 key No Deboucing Timer Is (are) the key(s) still released ? (*) Yes Figure 14: Keypad Interface Flow Chart Rev. 1.2 Keypad Initialization All Column Outputs = 0 Any Row ...
Page 70
Keypad Column Register (KCOL): 0xD1 This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. MSB – – ...
Page 71
Keypad Scan Time Register (KSCAN): 0xD3 This register contains the values of scanning time and debouncing time. MSB DBTIME.5 DBTIME.4 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0 Bit Symbol KSCAN.7 DBTIME.5 KSCAN.6 DBTIME.4 De-bounce time in 4ms increments 4ms ...
Page 72
Keypad Control/Status Register (KSTAT): 0xD4 This register is used to control the hardware keypad scanning and detection capabilities, as well as the keypad interrupt control and status. MSB – – Bit Symbol KSTAT.7 – KSTAT.6 – KSTAT.5 – KSTAT.4 – ...
Page 73
Keypad Scan Time Register (KSIZE): 0xD5 This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to VDD. MSB – – ROWSIZ.2 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 Defines the number of ...
Page 74
Keypad Column MS Scan Order Register (KORDERH): 0xD7 MSB – 5COL.2 5COL.1 Bit Symbol KORDERH.7 – KORDERH.6 5COL.2 KORDERH.5 5COL.1 Column to scan 5 KORDERH.4 5COL.0 KORDERH.3 4COL.2 KORDERH.2 4COL.1 Column to scan 4 KORDERH.1 4COL.0 KORDERH.0 3COL.2 Column to ...
Page 75
USB Interface The 73S1217F provides a single interface, full speed -12Mbps - USB device port as per the Universal Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the transceiver, the Serial Interface Engine (SIE), ...
Page 76
Data0/Data1 toggle synchronization, bit stuffing, bus idle detection and other protocol generation/checking required in Chapter 8 of the USB specification. The firmware is responsible for servicing and building the messages required under Chapter 9 of the ...
Page 77
Clock Control Register (CKCON): 0x8E MSB – – Bit Symbol CKCON.7 – CKCON.6 – CKCON.5 – CKCON.4 – CKCON.3 – These three bits determine the number of wait states (machine cycles) to insert when accessing the USB SFRs: CKCON.2 CKWT.2 ...
Page 78
Smart Card Interface Function The 73S1217F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 73S8010x family of ...
Page 79
The built-in ICC Interface has a linear regulator (V cards in accordance with the ISO 7816-3 and EMV4.0 standards. This converter uses the V nominal) input supply source. See the power supply management section above for more detail. Auxiliary I/O ...
Page 80
ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1217F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection ...
Page 81
Answer to Reset Processing A card insertion event generates an interrupt to the firmware, which is then responsible for the configuration of the electrical interface, the UART and activation of the card. The activation sequencer goes through the power ...
Page 82
Firmware sets VCCSEL delay or Card Event IO RST CLK CMDVCCnB VCC t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see t5, VCCOff_tmr) occurs until RST is ...
Page 83
F/D Register SCSel(3:2) SCCLK(5:0) SCSCLK(5:0) MCLK = 96MHz PLL Figure 20: Smart Card CLK and ETU Generation There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing parity error is ...
Page 84
Mode > EGT CHAR 1 < WWT WWT is set by the value in the BWT registers Mode TRANSMISSION (By seting Last_TXByte and TX/RXB=0 during CHAR N, BLOCK1 RX mode will start after last ...
Page 85
When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. The ...
Page 86
VCCSEL bits VCC VCCOK RSTCRD RST CLK IO t1 tto t1: The time from setting VCCSEL bits until VCCOK = 1. tto: The time from setting VCCSEL bits until VCCTMR times out (if RDYST = 1) or tto ...
Page 87
CLK Data from Card -end of ATR IO RLength Count - was set for length of ATR RLength Interrupt CLK Stop CLK Stop Level IO Bit IODir Bit TX/RX Mode Bit TX = '1' 1. Interrupt generated when Rlength counter ...
Page 88
CLK Data from Card IO (Bit 8) RLength Count Rlen=8 RLength = 9 RLength Interrupt RX data Protection Bit Data (Bit 9) TX/RX Mode Bit TX = '1' 1._ Interrupt generated when Rlength counter is Max CLK RLength Count Rlen=8 ...
Page 89
Smart Card SFRs Smart Card Select Register (SCSel): 0xFE00 The Smart Card Select register is used to determine which smart card interface is using the ISO UART. The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive ...
Page 90
Smart Card Interrupt Register (SCInt): 0xFE01 When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be ...
Page 91
Smart Card Interrupt Enable Register (SCIE): 0xFE02 When set to 1, the respective condition can cause a smart card interrupt. When set the respective condition cannot cause an interrupt. When disabled, the respective bit in the Smart ...
Page 92
Smart Card V Control/Status Register (VccCtl): 0xFE03 CC This register is used to control the power up and power down of the integrated smart card interface used to determine whether to apply 5V, 3V, or 1.8V to the ...
Page 93
V Stable Timer Register (VccTmr): 0xFE04 CC A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of ...
Page 94
Card Status/Control Register (CRDCtl): 0xFE05 This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register must be written to properly configure Debounce, Detect_Polarity (= 1), and the pull- up/down ...
Page 95
TX Control/Status Register (STXCtl): 0xFE06 This register is used to control transmission of data to the smart card. Some control and some status bits are in this register. MSB I2CMODE – TXFULL Bit Symbol I2C Mode – When in sync ...
Page 96
STX Data Register (STXData): 0xFE07 MSB STXDAT.7 STXDAT.6 STXDAT.5 Bit STXData.7 STXData.6 STXData.5 Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by the hardware and sent to the selected smart card. When ...
Page 97
SRX Control/Status Register (SRXCtl): 0xFE08 This register is used to monitor reception of data from the smart card. MSB BIT9DAT – Bit Symbol Bit 9 Data – When in sync mode and with MODE9/8B set, this bit will contain SRXCtl.7 ...
Page 98
SRX Data Register (SRXData): 0xFE09 MSB SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0 Bit SRXData.7 SRXData.6 SRXData.5 SRXData.4 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is ...
Page 99
Smart Card Control Register (SCCtl): 0xFE0A This register is used to monitor reception of data from the smart card. MSB RSTCRD – Bit Symbol 1 = Asserts the RST (set RST = 0) to the smart card interface ...
Page 100
External Smart Card Control Register (SCECtl): 0xFE0B This register is used to directly set and sample signals of External Smart Card interface. There are three modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ...
Page 101
C4/C8 Data Direction Register (SCDIR): 0xFE0C This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated. MSB – – Bit Symbol SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = ...
Page 102
Protocol Mode Register (SPrtcol): 0xFE0D This register determines the protocol to be use when communicating with the selected smart card. This register should be updated as required when switching between smart card interfaces. MSB SCISYN MOD9/8B SCESYN Bit Symbol Smart ...
Page 103
SC Clock Configuration Register (SCCLK): 0xFE0F This register controls the internal smart card (CLK) clock generation. MSB LSB – – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0 Bit Symbol SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 Internal Smart Card CLK Frequency Select ...
Page 104
Parity Control Register (SParCtl): 0xFE11 This register provides the ability to configure the parity circuitry on the smart card interface. The settings apply to both integrated smart card interfaces. MSB – DISPAR BRKGEN BRKDET RETRAN DISCRX Bit Symbol SParCtl.7 – ...
Page 105
Byte Control Register (SByteCtl): 0xFE12 This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is ...
Page 106
FD Control Register (FDReg): 0xFE13 MSB FVAL.3 FVAL.2 FVAL.1 Bit Symbol FDReg.7 FVAL.3 Refer to Table 99. This value is converted per the table to set the divide FDReg.6 FVAL.2 ratio used to generate the baud rate (ETU). Default, also ...
Page 107
Table 99: Divider Values for the ETU Clock Fi code 0000 Di 372 F→ code D↓ 0001 1 744 0010 2 372 0011 4 186 0100 8 93 1000 12 62 0101 16 47 1001 20 37 0110 32 23 ...
Page 108
CRC MS Value Registers (CRCMsB): 0xFE14 MSB CRC.15 CRC.14 MSB CRC.7 CRC.6 The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode (read value). The initial value of CRC ...
Page 109
Block Guard Time Register (BGT): 0xFE16 This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends ...
Page 110
Block Wait Time Registers (BWTB0): 0xFE1B 0xFE19 0x00, (BWTB3): 0xFE18 MSB BWT.7 BWT.6 MSB BWT.15 BWT.14 MSB BWT.23 BWT.22 MSB – – These registers (BWTB0, BWTB1, BWTB2, BWTB3) are used to set the Block Waiting Time(27:0) (BWT). All of these ...
Page 111
ATR Timeout Registers (ATRLsB): 0xFE20 MSB ATRTO.7 ATRTO.6 ATRTO.5 MSB ATRTO.15 ATRTO.14 ATRTO.13 These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading edge of the first character and leading edge of ...
Page 112
Data Sheet Shaded locations indicate functions that are not provided in sync mode. Name Address b7 SCSel FE00 SCInt FE01 WAITTO/ RLIEN SCIE FE02 WTOI/ RLIEN VccCtl FE03 VCCSEL.1 VccTmr FE04 CRDCtl FE05 DEBOUN STXCtl FE06 I2CMODE STXData FE07 ...
Page 113
VDD Fault Detect Function The 73S1217F contains a circuit to detect a low-voltage condition on the supply voltage V it will deactivate the active internal smart card interface when V register configures the V Fault threshold for the nominal ...
Page 114
Data Sheet 2 Application Schematics 2.1 Typical Application Schematic GND 4 GND GND 100k +5VDC VCC 6 GND C1 R5 0.1uF USB_CONN_4 200k Host ...
Page 115
D S_1 21 7F_002 2.2 Typical Application Schematic GND 4 GND GND 3 R18 R19 +5VDC VCC 6 GND C27 USB_CONN_4 0.1uF Figure 28: 73S1217F Typical Application Schematic (USB ...
Page 116
Electrical Specification 3.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to V Parameter DC Supply voltage Supply Voltage V ...
Page 117
Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The Row pins have 100KΩ pull-ups. Symbol Parameter Voh Output level, high Vol Output level, low Vih Input voltage, ...
Page 118
Oscillator Interface Requirements Symbol Parameter Low-Power Oscillator Requirements. No External Load Beside The Crystal And Capacitor Is Permitted On Xout32 Pxtal Power in crystal IIL Input Leakage Current High-frequency oscillator (XIN) Parameters. XIN is used as input for external ...
Page 119
USB Interface Requirements Parameter Receiver Parameters Differential input sensitivity Differential common mode range Single ended receiver threshold Transmitter Levels Low Level Output Voltage High Level Output Voltage Output Resistance (1) Driver output resistance PD Pullup Resistor (to VDD) Transceiver ...
Page 120
Parameter C = 50pf, series 24Ω, 1% source termination resistor included L Rise Time USBTR Fall Time USBTF Rise/fall time matching TRFM Output signal crossover VCRS voltage Source Jitter to Next TDJ1 Transition Source Jitter For Paired TDJ2 Transitions Receiver ...
Page 121
Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General conditions, -40°C < T < 85°C, 4.75V < V Card supply Voltage V including ripple and CC noise V V Ripple CCrip CC Card supply ...
Page 122
Symbol Parameter Interface Requirements – Data Signals: I/O, AUX1 and AUX2 V Output level, high OH V Output level, low OL V Input level, high IH V Input level, low IL Output voltage when outside V INACT of session I ...
Page 123
DC Characteristics Symbol Parameter Supply Current @ V (V and V unconnected) BUS BAT Supply Current @ V (V and V unconnected) BUS BAT I PC Supply Current @ V (V and V unconnected) BUS BAT Supply Current @ ...
Page 124
BUS Supply Current @ V 6. 0V) BUS V V Supply Voltage DD DD Supply Current I DD_IN (pins 28 and 40) Supply Current – pin 68 I (available to external DD_OUT circuitry) I ...
Page 125
Current Fault Detection Circuits Symbol Parameter IV V over current fault Pmax P I VDD over-current limit DDmax I Card overcurrent fault CCF I Card overcurrent fault CCF1P8 Rev. 1.2 Condition Min Typ 1.8V 60 ...
Page 126
Equivalent Circuits X12LIN ESD ENABLE ENABLEb X32LIN ESD 126 VDD Figure 29: 12 MHz Oscillator Circuit VDD >1MEG Figure 30: 32KHz Oscillator Circuit X12OUT ESD To circuit X32OUT ESD To circuit Rev. 1.2 ...
Page 127
Output Disable Data From circuit To circuit Output Disable Data From circuit Rev. 1.2 VDD STRONG PFET STRONG NFET Figure 31: Digital I/O Circuit VDD STRONG PFET STRONG NFET Figure 32: Digital Output Circuit PIN ESD PIN ESD 127 ...
Page 128
Pull-up Disable Output Disable Data From circuit To circuit Figure 33: Digital I/O with Pull Up Circuit Output Disable Data From circuit To circuit Pull-down Enable Figure 34: Digital I/O with Pull Down Circuit 128 VDD VERY WEAK PFET STRONG ...
Page 129
To circuit Pull-up Disable Output Disable Data From circuit To circuit Pull-down Enable Rev. 1.2 Figure 35: Digital Input Circuit STRONG PFET STRONG NFET Figure 36: OFF_REQ Interface Circuit PIN ESD VDD VERY WEAK PFET ESD PIN ESD VERY WEAK ...
Page 130
Pull-up Disable Output Disable Data From circuit To circuit Output Disable Data From circuit To circuit 130 STRONG PFET STRONG NFET Figure 37: Keypad Row Circuit VDD 1200 OHMS MEDIUM PFET STRONG NFET Figure 38: Keypad Column Circuit VDD 100k ...
Page 131
Pullup Disable Data From circuit To circuit Current Value Control PIN Figure 40: Test and Security Pin Circuit Rev. 1.2 VDD STRONG PFET STRONG NFET Figure 39: LED Circuit This buffer has a special input threshold: Vih>0.7*VDD ...
Page 132
From circuit 132 To Comparator Input PIN ESD Figure 41: Analog Input Circuit VCC Figure 42: Smart Card Output Circuit STRONG ESD PFET PIN ESD STRONG NFET Rev. 1.2 ...
Page 133
From circuit To circuit To circuit Pull-down Enable Rev. 1.2 STRONG PFET 125ns DELAY STRONG NFET Figure 43: Smart Card I/O Circuit VERY WEAK NFET Figure 44: PRES Input Circuit VCC RL=11K ESD IO PIN ESD VDD ESD PIN ESD ...
Page 134
RP_ENb DP_OUT DP_IN RCV_IN DM_IN DM_OUT OUTPUT ENABLEb PIN 134 VDD VDD ZOUT= 20Ω OUTPUT ENABLEb IN_P IN_N VDD ZOUT= 20Ω Figure 45: USB Circuit VPC R= 24kΩ ESD Figure 46: ON_OFF Input Circuit 1500 Ω DP ESD DM ESD ...
Page 135
Package Pin Designation (68-Pin QFN) TXD 18 COL4 19 USR7 20 ROW0 21 ROW1 22 USR6 23 ROW2 24 GND VDD 28 USR5 29 USR4 30 USR3 31 USR2 32 ROW3 33 USR1 34 ...
Page 136
Packaging Information .2 Packaging Information 68-Pin QFN Package Outline 68-Pin QFN Package Outline Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear ...
Page 137
... For more information about Teridian Semiconductor products or to check the availability of the 73S1217F, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices http://www.teridian.com. Rev. 1.2 Order Number Packaging Mark 73S1217F-68IM/F 73S1217F68IM 73S1217F-IMR/F 73S1217F68IM 137 ...
Page 138
Revision History Revision Date Description 1.0 5/15/2007 First publication. 1.1 11/7/2007 On protocols T=0, T=1” to “ISO-7816 UART for protocols T=0, T=1” references. In preferred location for the user’s preboot code, may not be page-erased by either MPT ...
Page 139
PGADDR (see detailed description above).” FUSECtl bit description to TRIMPCtl Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl, LEDCal and LOCKCtl registers the paragraphs about MPU clock rates ...
Page 140
Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. Signum Systems is a trademark of Signum Systems Corporation. All other trademarks are ...