73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 75

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the
1.7.16 USB Interface
The 73S1217F provides a single interface, full speed -12Mbps - USB device port as per the Universal
transceiver, the Serial Interface Engine (SIE), and the data buffers. An internal pull-up to V
indicates that the device is a full speed device attached to the USB bus (allows full speed recognition by
the host without adding any external components). When using the USB interface, V
3.0V – 3.6V in order to meet the USB VOH requirement. The interface is highly configurable under
3.0V – 3.6V in order to meet the USB VOH requirement. The interface is highly configurable under
firmware control. Control (Endpoint 0), Interrupt IN, Bulk IN and Bulk OUT transfers are supported. Four
firmware control. Control (Endpoint 0), Interrupt IN, Bulk IN and Bulk OUT transfers are supported. Four
endpoints are supported and are configured by firmware:
endpoints are supported and are configured by firmware:
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Figure 15 shows the simplified block diagram of the USB interface.
Figure 15 shows the simplified block diagram of the USB interface.
The USB interface consists of a Serial Interface Engine (SIE) that handles NRZI encoding/decoding, bit
stuffing / unstuffing, and CRC generation/checking. It also generates headers for packets to be
transmitted and decodes the headers of received packets. An analog transceiver interfaces with the
external USB bus. The USB interface hardware performs error checking and removes the USB protocol
fields from the incoming messages before passing the data to the firmware. The hardware also adds the
USB protocol fields to the outgoing messages coming from the firmware. The hardware implements
NRZI encoding/decoding, CRC checking/generation (both on data and token packets), device address
Rev. 1.2
Endpoint 0, the default (Control) endpoint as required by the USB specification, is used to exchange
Endpoint 0, the default (Control) endpoint as required by the USB specification, is used to exchange
control and status information between the 73S1217F and the USB host.
control and status information between the 73S1217F and the USB host.
Bulk IN Endpoint #1
Bulk IN Endpoint #1
Bulk OUT Endpoint #1
Bulk OUT Endpoint #1
Interrupt IN Endpoint #2
Interrupt IN Endpoint #2
The USB block contains several FIFOs used for communication.
The USB block contains several FIFOs used for communication.
There is a 128-byte RAM FIFO for each BULK endpoint. Maximum Bulk packet size is 64 bytes.
There is a 128-byte RAM FIFO for each BULK endpoint. Maximum Bulk packet size is 64 bytes.
There is a 32-byte RAM FIFO for the interrupt endpoint. Maximum Interrupt packet size is 16 bytes.
There is a 32-byte RAM FIFO for the interrupt endpoint. Maximum Interrupt packet size is 16 bytes.
There is a 16-byte RAM FIFO for the control endpoint. Maximum Control packet size is 16 bytes.
There is a 16-byte RAM FIFO for the control endpoint. Maximum Control packet size is 16 bytes.
D+
D-
VDD
Transceivers
MISCtl1
MISCtl1
0
1
Figure 15: USB Block Diagram
USBCon
USBPEN
USB Registers
Full Speed
Interface
12Mbps
Engine
Serial
USB
48MHz
Clock
Control Endpoint 0
Bulk IN Endpoint 1
Bulk OUT Endpoint 1
Interrupt IN Endpoint 2
128-Byte FIFO
128-Byte FIFO
16-Byte FIFO
32-Byte FIFO
DD
must be between
must be between
DD
on D+
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