xr16m580im48 Exar Corporation, xr16m580im48 Datasheet - Page 29

• Manufacturer Part Number: xr16m580im48
• Description: 1.62v To 3.63v High Performance Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
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ISR[0]: Interrupt Status
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ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[4]: Interrupt Status (requires EFR bit-4 = 1)
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff, Xon or special character(s).
ISR[5]: Interrupt Status (requires EFR bit-4 = 1)
ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
P
Special character interrupt is cleared by a read to ISR register or after next character is received. See
EMSR[7].
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wakeup interrupt is cleared by a read to ISR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
L
RIORITY
EVEL
1
2
3
4
5
6
7
-
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
EGISTER
IT
T
0
1
0
0
0
0
0
0
ABLE
-3
B
8: I
S
IT
TATUS
1
1
1
0
0
0
0
0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
29
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xon, Xoff or Special character)
CTS#, RTS# change of state
None (default) or Wakeup interrupt
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
XR16M580
Table
8).