xr16m681 Exar Corporation, xr16m681 Datasheet
xr16m681
Available stocks
Related parts for xr16m681
xr16m681 Summary of contents
Page 1
... An internal loopback capability allows onboard diagnostics. The M681 is available in 24-pin QFN, 32-pin QFN and 25-pin BGA packages OTE 1 Covered by U.S. Patent #5,649,122 XR16M681 B D IGURE LOCK IAGRAM Pw rSave LLA# AD7:AD0 IOR# IOW # ...
Page 2
... QFN AD2 22 23 AD3 AD4 Corner CTS# VCC AD0 AD3 AD4 ORDERING INFORMATION P N ART UMBER XR16M681IL24 XR16M681IL32 XR16M681IB25 IOR# 12 DSR# 25 GND CD RI IOW# VCC 28 9 XTAL2 AD0 29 8 XTAL1 30 AD1 7 ...
Page 3
... UART Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6]. This pin can also be used as the Auto RS-485 Half-duplex Direction control output, see FCTR[3] and EMSR[3]. 3 XR16M681 D ESCRIPTION ...
Page 4
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE Pin Description 24-QFN 32-QFN 25-BGA N AME P # PIN CTS DTR DSR CD RI ANCILLARY SIGNALS XTAL1 8 10 XTAL2 9 11 PwrSave 7 9 RESET VCC 19 28 GND 11 13 GND Center Center ...
Page 5
... CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps. The XR16M681 can operate from 1.62 to 3.63 volts. The M681 is fabricated with an advanced CMOS process. ...
Page 6
... The CPU interface is a VLIO bus interface. The VLIO bus interface is an 8-bit multiplexed address/data bus interface. Each bus cycle is asynchronous using CS#, LLA# and IOR# or IOW# inputs. A typical data bus interconnection for the VLIO bus interface is shown XR16M681 T VLIO D IGURE YPICAL ...
Page 7
... Serial Interface The M681 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com or send an e-mail to uarttechsupport@exar.com XR16M681 T S IGURE YPICAL ERIAL ...
Page 8
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE F 5. XR16M681 T S IGURE YPICAL ERIAL UART DTR NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# DSR# CD GND RS-485 Half-Duplex Serial Interface ...
Page 9
... HIGH = FIFO below trigger level or FIFO empty 2: INT PERATION FOR ECEIVER ) FCR B ISABLED LOW = FIFO below trigger level HIGH = FIFO above trigger level or RX Data Timeout 9 XR16M681 23. Table 1 and 2 Figure 19 through 22 (FIFO NABLED - (FIFO NABLED ...
Page 10
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 2.6 Crystal Oscillator or External Clock Input The M681 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock for bus operation ...
Page 11
... Independent TX/RX BRG The XR16M681 has two independent sets of TX and RX baud rate generator. See work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting, please See ” ...
Page 12
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate ...
Page 13
... IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock ( DLD[5:4] ) 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M681 TXNOFIFO1 ...
Page 14
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty ...
Page 15
... FIFO trigger level. FIFO is Enabled bit-0=1 D ata fills to R TS# de-asserts w hen data fills above the flow 24 control trigger level to suspend rem ote transm itter. Enable by EFR bit-6= bit-1. R eceive D ata 15 XR16M681 Receive Data Characters RXFIFO1 M ODE R eceive D ata C haracters R XFIFO 1 ...
Page 16
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...
Page 17
... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 17 XR16M681 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
Page 18
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M681 will halt transmission (TX) as soon as the current character has completed transmission ...
Page 19
... Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE Figure 13 below. 19 XR16M681 Figure 13. ...
Page 20
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE F 13 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and Power-Save feature The M681 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save feature is included to reduce its power consumption when the chip is not actively used ...
Page 21
... The M681 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The default status of wake up interrupt is disabled. Please Write-Only” on page 29. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE Figure 1 on page See ”Section 4.5, FIFO Control Register (FCR XR16M681 1) from other bus activities that ...
Page 22
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 2.18 Internal Loopback The M681 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
Page 23
... Read-only E R NHANCED EGISTERS Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 23 XR16M681 /W C RITE OMMENTS LCR[ LCR ≠ 0xBF, DLL = 0x00, DLM = 0x00 LCR[ LCR ≠ 0xBF See DLD[7:6] LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR[ EFR[ LCR ≠ 0xBF if EFR[ LCR ≠ ...
Page 24
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO ...
Page 25
... ISR [5:4], Flow FCR[5:3], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 25 XR16M681 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 LCR[ LCR≠0xBF DLL= 0x00 ...
Page 26
... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M681 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
Page 27
... CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control. • RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control. • Wakeup interrupt is generated when the M681 wakes up from the sleep mode. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 27 XR16M681 ...
Page 28
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading RHR. ...
Page 29
... Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 21. Table 9 below shows the selections. Note that the Table 9 29 XR16M681 shows the complete selections. ...
Page 30
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE ABLE RANSMIT AND FCR B -7 FCR B -6 FCR 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
Page 31
... Logic 1 = Divisor latch registers are selected. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE T 10: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 31 XR16M681 ...
Page 32
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • ...
Page 33
... Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE Figure 33 XR16M681 14. ...
Page 34
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “ ...
Page 35
... MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M681. Lower four bits of this register are reserved. Writing to the higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter (Requires EFR[ • ...
Page 36
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 4.12 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in ...
Page 37
... Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for TX. Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for RX. Transmitter and Receiver uses same BRG. 37 XR16M681 See ”Section 2.7, Programmable Table 13 below ...
Page 38
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE 4.14 Trigger Level Register (TRG) - Write-Only User Programmable Transmit/Receive Trigger Level Register. TRG[7:0]: Trigger Level Register These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1). ...
Page 39
... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 39 XR16M681 ECEIVE OFTWARE LOW ONTROL ...
Page 40
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘ ...
Page 41
... Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 7-0 =0xX0 (Read-only) Bits 7-4 = 0000 (Write-only) Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 RESET STATE HIGH HIGH HIGH Three-State Condition 41 XR16M681 ...
Page 42
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (24-QFN) Thermal Resistance (32-QFN) Thermal Resistance (25-BGA) ELECTRICAL CHARACTERISTICS ...
Page 43
... XR16M681 L L IMITS IMITS 3.3V ± 10% U NIT MHz 64 80 MHz ...
Page 44
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay From IOR# To Reset RXRDY Delay From IOW# To Set TXRDY Delay From Center of Start To Reset SRT TXRDY# T Reset Pulse Width ...
Page 45
... Upper Address AD0 T AS CS# T CSL LLA# IOW# 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE Lower Address LLA CSL T RDV T LLAR T RD Lower Address Data LLA DS T CSL T LLAW XR16M681 Data ...
Page 46
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE F 19 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* ...
Page 47
... SSI RX FIFO fills Trigger Level or RX Data Timeout T [FIFO M ] IMING ODE Stop Bit D0:D7 D0:D7 T D0: WRI 47 XR16M681 S D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA# Last Data Byte Transmitted D0:D7 D0: ISR is read ...
Page 48
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE PACKAGE DIMENSIONS (24 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.154 0.161 3 ...
Page 49
... INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 0.150 3.50 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.012 0.020 0.35 0.008 - 0.20 49 XR16M681 Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm MAX 1.00 0.05 0.25 5.10 3.80 0.30 0.45 - ...
Page 50
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE PACKAGE DIMENSIONS (25 PIN BGA - 0.8 Seating Plane Note: The control dimension is the millimeter column SYMBOL (A1 corner feature is mfger option INCHES ...
Page 51
... XR16M681 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE REVISION HISTORY D R ATE EVISION February 2009 Rev 1.0.0 Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...