xr16m681 Exar Corporation, xr16m681 Datasheet - Page 3

• Manufacturer Part Number: xr16m681
• Description: 1.62v To 3.63v Uart With 32-byte Fifo And Vlio Interface
• Manufacturer: Exar Corporation

REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
IOW#
RTS#
N
IOR#
LLA#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CS#
INT
TX
RX
AME
24-QFN
P
20
21
22
23
24
12
10
14
15
16
IN
1
2
3
6
5
4
#
32-QFN
PIN#
29
30
31
32
14
12
19
20
21
1
3
4
5
8
7
6
25-BGA
P
C1
D2
D1
C2
D3
C3
E2
E1
B2
E3
A5
E5
A4
B4
E4
A3
IN
#
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
T
I/O
YPE
O
O
O
I
I
I
I
I
Multiplexed Address/Data lines [7:0]. The register address is
latched on the rising edge of the LLA#. After the LLA# signal goes
high, the UART enters the data phase where the data is placed on
these lines.
Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
Interrupt output (active high). The output state is defined by the
user through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6]. This pin can also be used as the
Auto RS-485 Half-duplex Direction control output, see FCTR[3] and
EMSR[3].
3
D
ESCRIPTION
XR16M681