xr16v2750 Exar Corporation, xr16v2750 Datasheet - Page 51

• Manufacturer Part Number: xr16v2750
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.3
GENERAL DESCRIPTION................................................................................................ 1
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8
3.0 UART INTERNAL REGISTERS............................................................................................................. 22
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 24
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE ................................................................................................................................................ 8
2.2 5-VOLT TOLERANT INPUTS .............................................................................................................................. 8
2.3 DEVICE RESET ................................................................................................................................................... 8
2.4 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 8
2.5 CHANNEL A AND B SELECTION ...................................................................................................................... 8
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................... 9
2.7 DMA MODE ......................................................................................................................................................... 9
2.8 INTA AND INTB OUTPUTS............................................................................................................................... 10
2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 10
2.10 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ......................................... 11
2.11 TRANSMITTER................................................................................................................................................ 13
2.12 RECEIVER ....................................................................................................................................................... 14
2.13 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 16
2.14 AUTO RTS HYSTERESIS .............................................................................................................................. 16
2.15 AUTO CTS FLOW CONTROL........................................................................................................................ 16
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 18
2.17 SPECIAL CHARACTER DETECT.................................................................................................................. 18
2.18 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 18
2.19 INFRARED MODE ........................................................................................................................................... 19
2.20 SLEEP MODE WITH AUTO WAKE-UP ......................................................................................................... 20
2.21 INTERNAL LOOPBACK................................................................................................................................. 21
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 24
F
F
F
T
T
T
T
F
F
T
F
F
F
F
F
T
F
F
T
T
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 13
2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 13
2.11.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 13
2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 14
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 25
1: C
2: TXRDY#
3: INTA
4: INTA
5: T
6: A
7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 22
8: INTERNAL REGISTERS DESCRIPTION. S
1. XR16V2750 B
2. P
3. XR16V2750 D
4. T
5. B
6. T
7. T
8. R
9. R
10. A
11. I
12. I
.................................................................................................................................................... 1
YPICAL DATA RATES WITH A
HANNEL
UTO
YPICAL OSCILLATOR CONNECTIONS
RANSMITTER
RANSMITTER
IN
AUD
ECEIVER
ECEIVER
NFRARED
NTERNAL
UTO
.............................................................................................................................................. 1
O
AND
AND
X
UT
R
ON
RTS
ATE
A
AND
A
INTB P
INTB P
/X
SSIGNMENT
O
O
AND
L
OFF
T
G
PERATION IN NON
PERATION IN
OOP
AND
RANSMIT
RXRDY# O
ENERATOR
O
O
LOCK
ATA
............................................................................................................................... 2
B S
PERATION IN NON
PERATION IN
(S
INS
IN
CTS F
B
OFTWARE
ACK IN
B
ELECT
O
D
US
O
PERATION
..................................................................................................................................................... 2
IAGRAM
D
PERATION FOR
ATA
I
LOW
NTERCONNECTIONS
............................................................................................................................................... 12
FIFO
UTPUTS IN
C
............................................................................................................................................... 9
24 MH
) F
HANNEL
E
FIFO
C
-FIFO M
NCODING AND
......................................................................................................................................... 1
LOW
ONTROL
TABLE OF CONTENTS
AND
F
OR
-FIFO M
Z CRYSTAL OR EXTERNAL CLOCK AT
AND
............................................................................................................................... 10
C
A
FIFO
A
R
UTO
ONTROL
T
ODE
ECEIVER
AND
RANSMITTER
O
F
LOW
PERATION
ODE
AND
RTS F
.................................................................................................................... 15
B ................................................................................................................ 21
R
................................................................................................................... 8
HADED BITS ARE ENABLED WHEN
ECEIVE
C
.............................................................................................................. 13
............................................................................................................... 18
DMA M
ONTROL
............................................................................................................. 10
LOW
....................................................................................................... 17
...................................................................................................... 10
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
I
D
C
ODE
ATA
ONTROL
M
ODE
D
............................................................................................. 9
ECODING
..................................................................................... 14
M
ODE
16X S
.......................................................................... 19
......................................................................... 15
AMPLING
EFR B
IT
................................................... 12
-4=1 ......................................... 23
XR16V2750