xr16l2751im Exar Corporation, xr16l2751im Datasheet
xr16l2751im
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xr16l2751im Summary of contents
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OCTOBER 2005 GENERAL DESCRIPTION 1 The XR16L2751 (2751 low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device includes 2 additional capabilities XR16L2750: Intel and Motorola data bus selection and a ...
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... TXB OP2B# CSA# CSB# PWRSAVE RXB RXA TXRDYB# TXA TXB OP2B# CS# A3 PWRSAVE ORDERING INFORMATION ART UMBER ACKAGE XR16L2751CM 48-Lead TQFP XR16L2751IM 48-Lead TQFP XR16L2751 6 48-pin TQFP 7 (16 Mode ) XR16L2751 6 48-pin TQFP 7 ...
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REV. 1.2.2 PIN DESCRIPTIONS Pin Description 48-TQFP N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE Pin Description 48-TQFP N T AME YPE INTB 29 O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel B inter- rupt output. ...
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REV. 1.2.2 Pin Description 48-TQFP N T AME YPE TXB 8 O UART channel B Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[ this mode, the ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE Pin Description 48-TQFP N T AME YPE HDCNTL Auto RS-485 half-duplex direction output enable for channel A and B (active low). Connect this pin to ...
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REV. 1.2.2 auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has to set FCTR[ This pin is normally high for receive state, low for transmit state. Data Bus ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The ...
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REV. 1.2.2 2.2 5-Volt Tolerant Inputs The 2751 can accept inputs when operating at 3.3V or 2.5V. But note that if the 2751 is operating at 2.5V, its V may not be high enough to meet ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE Beyond the general 16C2550 features and capabilities, the 2751 offers enhanced feature registers (EFR, Xon/ Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR, FC) that provide automatic RTS and CTS hardware ...
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REV. 1.2.2 2.9 Crystal Oscillator or External Clock Input The 2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 2.10 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL hardware pin or a software bit in ...
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REV. 1.2.2 2.11 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal clock. ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE IGURE RANSMITTER Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X Clock (EMSR ...
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REV. 1.2 IGURE ECEIVER PERATION IN NON 16X or 8X Clock (EMSR bit-7) Receive Data Byte and Errors F 10 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 64 bytes ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote ...
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REV. 1.2.2 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# TXB Data Starts RXA ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the ...
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REV. 1.2.2 2.18 Auto RS485 Half-duplex Control The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-3. By default, it de-asserts RTS# (HIGH) output following the last stop bit of the last ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 2.20 Sleep Mode with Wake-Up Indicator and PowerSave Feature The 2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave feature is included to reduce ...
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REV. 1.2.2 2.21 Internal Loopback The 2751 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 13 ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2751 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or ...
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REV. 1.2 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit ...
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REV. 1.2.2 B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt ...
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REV. 1.2 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 ...
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REV. 1.2.2 T 11: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table-C ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 LCR[3]: TX and RX Parity ...
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REV. 1.2.2 LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW state). This condition remains, until disabled by setting LCR bit-6 to ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE MCR[6]: Infrared Encoder/Decoder Enable • Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default) • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The ...
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REV. 1.2.2 LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# ...
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REV. 1.2.2 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (for 16C2550 ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 4.15 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should ...
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REV. 1.2.2 FCTR[6]: Scratchpad Swap • Logic 0 = Scratchpad register is selected as general read and write register. ST16C550 compatible mode. • Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of characters in ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying ...
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REV. 1.2.2 T 17: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM and DLL Bits 15-0 = 0x0001. Only resets during a power up. It doesn’t reset when the Reset Pin is asserted. RHR Bits 7-0 ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation ELECTRICAL CHARACTERISTICS TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) DC ELECTRICAL CHARACTERISTICS O ...
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REV. 1.2.2 For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. PAGE 20. AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Delay From IOW# To Output WDO T Delay To ...
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REV. 1.2 IGURE ODEM NPUT UTPUT IOW # Active IOW RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ODE NTEL ATA A0-A2 Valid ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE F 17 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- IGURE ODE OTOROLA ...
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REV. 1.2 IGURE ODE OTOROLA A0-A2 T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE F 21 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading ...
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REV. 1.2 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE F 25 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0: D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data ...
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REV. 1.2.2 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL 2.25V TO ...
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... EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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REV. 1.2.2 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................. 1 EATURES F 1. XR16L2751 B D ................................................................................................................................................. 1 IGURE LOCK IAGRAM ............................................................................................................................................................. 2 IGURE IN UT SSIGNMENT ............................................................................................................................. 2 ORDERING INFORMATION PIN ...
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XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 4.0 INTERNAL Register descriptions ........................................................................................ 24 4 ECEIVE OLDING EGISTER 4 RANSMIT OLDING EGISTER 4 NTERRUPT NABLE EGISTER 4.3.1 IER versus ...