xr20m1172 Exar Corporation, xr20m1172 Datasheet
xr20m1172
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xr20m1172 Summary of contents
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... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Battery-Operated Devices • Cellular Data Devices • Factory Automation and Process Controls F 1. XR20M1172 B D IGURE LOCK IAGRAM – ...
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... VCC A0/CS# A1/ SI I2C/SPI# SO SDA RXB RXA TXA TXB XTAL1 XTAL2 GPIO2/CDB# GND ORDERING INFORMATION ART UMBER XR20M1172IL32 32-pin QFN XR20M1172IG28 28-Lead TSSOP 32-pin QFN 29 VCC XTAL2 ...
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... See IOControl[1] and IODir register. O UART Request-To-Send. This output can be used for Auto RTS Hard- ware Flow Control, Auto RS-485 Half-Duplex direction control general purpose output. If unused, this pin should be left uncon- nected. 3 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO Pin Description 32-QFN 28-TSSOP N AME CTSB SCL 17 19 ENIR EN485 IRQ RTSA GPIO5/DTRA GPIO1/DTRB RESET CTSA GPIO4/DSRA GPIO6/CDA YPE ESCRIPTION I UART Clear-To-Send. This input can be used for Auto CTS Hardware Flow Control general purpose input ...
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... PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad Connection. 5 XR20M1172 2 C-bus config- 2 C-bus 2 C-bus interface is selected if this pin ...
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... FIFO trigger levels, infrared encoder and decoder (IrDA 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps with 4X sampling clock rate. The XR20M1172 is a 1.62V to 3.63V device. The M1172 is fabricated with an advanced CMOS process. ...
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... C-bus master contains a start bit (SDA transition from HIGH to LOW Figures (M1172) REGISTER nDATA ADDRESS (M1172) SLAVE ADDRESS 7 XR20M1172 2 2 C-bus specifications. The C-bus master is a stop bit (SDA below. For complete details, see the P STOP condition A P nDATA A LAST DATA NA P ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO IGURE ATA ORMATS SLAVE Master write: ADDRESS START condition write acknowledge SLAVE Master read: ADDRESS START condition read acknowledge SLAVE Combined S R/W A formats: ADDRESS Read or START condition acknowledge ...
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... UART Channel A ’01’ = UART Channel B other values are reserved 0 Reserved After the last read or write transaction, the I TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2 C-bus. To distinguish itself from the other devices on the XR20M1172 ABLE DDRESS DDRESS ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.1.2 SPI Bus Interface The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input (SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI mode, the CS# signal for the M1172 is asserted by the SPI master, then the SPI master starts toggling the SCL signal with the appropriate transaction information ...
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... HIGH = FIFO above trigger level LOW = FIFO below trigger level or transmitter empty 5: IRQ PERATION OR ECEIVER ) (FIFO E HIGH = FIFO below trigger level LOW = FIFO above trigger level 11 XR20M1172 last bit 24. Table 4 Figures 21 through 35 (FIFO NABLED FCR B ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.5 Crystal Oscillator or External Clock Input The M1172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART ...
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... TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 Fractional Baud Rate Generator Logic Prescaler Divide by 4 MCR Bit-7=1 13 XR20M1172 16X Sampling Rate Clock to Transmitter and Receiver ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 150 19200 78.125 25000 60 28800 52.0833 38400 39.0625 50000 ...
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... Transmit Shift Register (TSR FIFO AND LOW ONTROL ODE Transmit THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transm it Data Shift Register (TSR) 15 XR20M1172 TXNOFIFO1 TXFIFO 1 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.8 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate ...
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... RHR Interrupt (ISR bit-2) programmed for Trigger=16 desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to RTS# de-asserts when data fills to the Halt Level Halt Level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data Figure 17): 17): 17 XR20M1172 M ODE Receive Data Characters RXFIFO1 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. F 17. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO ...
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... If the address does not match its slave address, then the receiver should be disabled. TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO (See Table 15), the M1172 compares one or two sequential receive Table 19 XR20M1172 4). When idle, the auto RS485 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.14.2 Auto Address Detection Auto address detection mode is enabled when EFCR bit and EFR bit The desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address byte that matches the porgrammed character in the XOFF2 register ...
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... Figure 18 below RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 or 1/4 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 21 XR20M1172 Figure 18 ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder-1 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.16 Sleep Mode with Auto Wake-Up The M1172 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for both channels of the M1172 to enter sleep mode: no interrupts pending (ISR bit ■ ...
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... F 19 IGURE NTERNAL OOP Transmit Shift Register Receive Shift Register TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO B ACK VCC (THR/FIFO bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD# 23 XR20M1172 TX RX RTS# CTS# DTR# DSR# RI# CD# ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS The complete register set is shown below UART INTERNAL REGISTER ADDRESSES ABLE A DDRESS 0X00 RHR - Receive Holding Register THR - Transmit Holding Register 0X00 DLL - Divisor LSB 0X01 DLM - Divisor MSB ...
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... Bit-2 Bit-1 Bit-0 Bit-3 RX Trig RX Trig TX Trig Bit-2 Bit-1 Bit-0 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 25 XR20M1172 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX Data Stat ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x0B IOState RD/WR Bit-7 0x0C IOIntEna RD/WR Bit-7 0x0D reserved - 0 0x0E IOControl RD/WR 0 0x0F EFCR RD/WR Fast IR Mode 0x00 DLL RD/WR Bit-7 0x01 DLM RD/WR Bit-7 0x02 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR20M1172 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details. IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • ...
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... RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register GPIO (General Purpose Inputs RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 29 XR20M1172 L EVEL S OURCE OF INTERRUPT Table 9). ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered) ...
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... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO BIT-0 W ORD LENGTH (default TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7 1-1/2 6,7,8 2 (default) 31 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • ...
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... EGISTER AT DDRESS FFSET X Modem Status Register (MSR) 0 Modem Status Register (MSR) 1 Trigger Control Register (TCR) 13 EGISTER AT DDRESS FFSET MCR[2] Register at Address Offset 0x7 X Scratchpad Register (SPR) 0 Scratchpad Register (SPR) 1 Trigger Level Register (TLR) Figure 33 XR20M1172 19. “Section 2.15, ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit) • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). ...
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... MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 35 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. ...
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... If the input pin goes back to its initial logic state before the interrupt register is read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value that generated the interrupt. TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 37 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 4.19 Extra Features Control Register (EFCR) - Read/Write EFCR[7]: IrDA mode This bit selects between the slow and fast IrDA modes. See complete details. • Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps • ...
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... Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 39 XR20M1172 Table 14 below AMPLING ATE 16X 8X 4X ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR, TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values ...
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... Bits 7-4 = Logic levels of the inputs inverted [1] Bits 7-0 = 0xFF Bits 7-0 = 0x0F Bits 7-0 = 0x00 Bits 7-0 = 0x40 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 RESET STATE HIGH HIGH HIGH HIGH HIGH 41 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (32-QFN) Thermal Resistance (28-TSSOP) DC ELECTRICAL CHARACTERISTICS o o TA= -40 to +85 C, Vcc is 1 ...
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... VIHCK External Clock VILCK TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO o C, Vcc=1.62 - 3.63V L IMITS 1.8V ± 10% 2.5V ± 10 ECLK T ECH 43 XR20M1172 L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ECL ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL f Operating frequency SCL T Bus free time between STOP and START BUF T START condition hold time HD;STA T START condition setup time SU;STA T Data hold time HD ...
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... SLAVE SDA ADDRESS GPIOn TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO T D15 Bit 7 Bit 0 Bit 6 MSB LSB (A6) (A7) (R/W) T HIGH 1/F SCL SU;DAT HD;DAT W A IOSTATE REG XR20M1172 STOP Acknowledge condition (A) ( VD;DAT VD;ACK SU;STO DATA ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 24 IGURE ODEM NPUT IN NTERRUPT SLAVE SDA W ADDRESS IRQ MODEM pin F 25. GPIO P I IGURE IN NTERRUPT SLAVE SDA W A ADDRESS IRQ# GPIOn SLAVE A MSR REGISTER A S ADDRESS ACK from slave SLAVE IOSTATE REG ...
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... IRQ IGURE RANSMIT NTERRUPT SLAVE SDA W ADDRESS IRQ# TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO SLAVE RHR A S ADDRESS LEAR A THR REGISTER A DATA 47 XR20M1172 Next start Stop bit bit DATA DATA ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL T CS# HIGH to SO three-state time TR T CS# to SCL setup time CSS T CS# to SCL hold time CSH T SCL fall to SO valid time SCL setup time ...
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... GPIOx F 31. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R DTR# (GPIO5) TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO S UTPUT WITCH A0 CH1 CH0 UTPUT WITCH A0 CH1 CH0 XR20M1172 D10 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 32. SPI W THR C IGURE RITE TO LEAR CS# SCLK SI R GPIOx IRQ# F 33. R MSR C M IGURE EAD TO LEAR CS# SCLK SI R IRQ# TX INT A0 CH1 CH0 INT ODEM A0 CH1 CH0 D12 50 REV ...
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... LEAR CS# SCLK SI R IRQ# F 35. R RHR C RX INT IGURE EAD TO LEAR CS# SCLK SI R IRQ# TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO GPIO INT A0 CH1 CH0 D13 A0 CH1 CH0 D14 51 XR20M1172 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 0.150 3 ...
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... TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO ) INCHES MILLIMETERS MIN MAX MIN 0.033 0.047 0.85 0.002 0.006 0.05 0.031 0.041 0.80 0.007 0.012 0.19 0.004 0.008 0.09 0.378 0.386 9.60 0.248 0.260 6.30 0.169 0.177 4.30 0.0256 BSC 0.65 BSC 0.018 0.030 0.45 0° 8° 0° 53 XR20M1172 C A α L MAX 1.20 0.15 1.05 0.30 0.2 9.80 6.60 4.50 0.75 8° ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO REVISION HISTORY D R ATE EVISION September 2006 P1.0.0 Preliminary Datasheet. February 2007 P1.0.1 Updated Thermal Resistance Data. June 2007 1.0.0 Final Datasheet. Clarified pin descriptions. Updated DC Electrical Specifications. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability ...
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... LAVE IGURE ASTER EADS ROM LAVE F 6. I2C D F ........................................................................................................................................................ 8 IGURE ATA ORMATS 2.1.1.1 I2C- A BUS DDRESSING T 1: XR20M1172 I2C A M ABLE DDRESS T 2: I2C ABLE UB DDRESS EGISTER 2.1.2 SPI BUS INTERFACE ................................................................................................................................................... SPI ................................................................................................................................................ 10 ABLE IRST YTE ORMAT F 7 ...
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... XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. S ABLE 4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 26 4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 26 4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 26 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 26 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 27 4 ...
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... REV. 1.0.0 TABLE OF CONTENTS ..................................................................................................... TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO III XR20M1172 I ...