xr20m1172 Exar Corporation, xr20m1172 Datasheet - Page 11

• Manufacturer Part Number: xr20m1172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see
in the device.
The M1172 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the M1172 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, automatic RS-485 half-
duplex direction output enable/disable, TX and RX FIFO level counters, and programmable FIFO trigger level
control. For complete details, see
The IRQ# interrupt output changes according to the operating mode and enhanced features setup.
and 5
F
2.2
2.3
2.4
IGURE
IRQ# Pin
IRQ# Pin
IRQ# Pin
Table
summarize the operating behavior for the transmitter and receiver. Also see
10. SPI FIFO R
Device Reset
Internal Registers
IRQ# Output
16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
SCLK
Auto RS485
R/W A3
HIGH = no data
LOW = 1 byte
Mode
YES
NO
A2
EAD
(FIFO D
FCR B
A1
A0 CH1 CH0 X
T
HIGH = a byte in THR
LOW = THR empty
HIGH = a byte in THR
LOW = transmitter empty
IT
ISABLED
ABLE
T
-0 = 0
ABLE
“Section 3.0, UART Internal Registers” on page
(FIFO D
FCR B
4: IRQ# P
)
5: IRQ# P
D7
D6
IT
ISABLED
-0 = 0
D5
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
IN
D4
IN
O
)
D3
O
PERATION FOR
PERATION
11
D2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
D1
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or transmitter empty
D0
D7
F
OR
D6
T
RANSMITTER
R
D5
FCR B
ECEIVER
(FIFO E
FCR B
D4
D3
IT
-0 = 1 (FIFO E
D2
IT
NABLED
-0 = 1
D1
Figures 21 through
D0
)
24.
last bit
NABLED
XR20M1172
)
Table 4
35.