ICS8305 Integrated Circuit System, ICS8305 Datasheet

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ICS8305

Manufacturer Part Number
ICS8305
Description
Manufacturer
Integrated Circuit System
Datasheet
G
tial or single ended input levels. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin. Outputs
are forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or high
impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305 ideal for those applications demanding well de-
fined performance and repeatability.
B
8305AG
HiPerClockS™
,&6
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
CLK_EN
nCLK
CLK
D
OE
The ICS8305 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The ICS8305 has
selectable clock inputs that accept either differen-
IAGRAM
D
ESCRIPTION
0
1
0
1
D
LE
Q
www.icst.com/products/hiperclocks.html
Q0
Q1
Q2
Q3
LVCMOS-
L
OW
1
F
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential
• LVCMOS_CLK supports the following input types:
• Maximum output frequency: 350MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 700ps (maximum)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
P
S
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS, LVTTL
EATURES
IN
KEW
A
TO
4.4mm x 3.0mm x 0.92mm package body
, 1-
SSIGNMENT
-LVCMOS/LVTTL F
LVCMOS_CLK
TO
CLK_SEL
CLK_EN
-4, M
nCLK
GND
CLK
V
OE
16-Lead TSSOP
DD
G Package
ICS8305
Top View
ULTIPLEXED
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
Q1
GND
Q2
V
Q3
GND
DDO
DDO
ANOUT
D
ICS8305
IFFERENTIAL
REV. A JUNE 27, 2003
B
UFFER
/

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ICS8305 Summary of contents

Page 1

... LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well de- fined performance and repeatability ...

Page 2

... www.icst.com/products/hiperclocks.html 2 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT . ...

Page 3

... CLK_EN T D IGURE IMING IAGRAM www.icst.com/products/hiperclocks.html 3 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT ...

Page 4

... www.icst.com/products/hiperclocks.html 4 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT 70° ...

Page 5

... www.icst.com/products/hiperclocks.html 5 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT ...

Page 6

... www.icst.com/products/hiperclocks.html 6 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT 70° ...

Page 7

... ORE V DD SCOPE nCLK CLK GND C D EST IRCUIT IFFERENTIAL PART 1 Qx PART ART TO ART www.icst.com/products/hiperclocks.html 7 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT NFORMATION SCOPE UTPUT OAD EST IRCUIT Cross Points I L NPUT EVEL V DDO 2 V DDO ...

Page 8

... ROPAGATION ELAY V DDO 2 Q0:Q3 Pulse Width t PERIOD t PW odc = t PERIOD odc & ERIOD 8305AG - KEW TO LVCMOS- -LVCMOS/LVTTL F TO 20% Clock Outputs UTPUT ISE ALL www.icst.com/products/hiperclocks.html 8 ICS8305 D ULTIPLEXED IFFERENTIAL B ANOUT UFFER 80% 80% 20 IME REV. A JUNE 27, 2003 / ...

Page 9

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K CLK V_REF nCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 9 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT UFFER = 3.3V, V_REF should be 1.25V DD I NPUT REV. A JUNE 27, 2003 / ...

Page 10

... HiPerClockS Input 3D. H NPUT RIVEN BY IGURE 3.3V R4 125 CLK nCLK HiPerClockS Input NPUT RIVEN OUPLE www.icst.com/products/hiperclocks.html 10 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK/ CLK ...

Page 11

... S E CHEMATIC XAMPLE This application note provides general design guide using ICS8305 LVCMOS buffer. Figure 3 shows a schematic example of the ICS8305 LVCMOS clock buffer. In this example, the input VDD VDD Ohm R3 43 3,.3V LVCMOS IGURE XAMPLE 8305AG ...

Page 12

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8305 is: 459 8305AG KEW ...

Page 13

... ° 0 ° Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html 13 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT UFFER m REV. A JUNE 27, 2003 / ...

Page 14

... www.icst.com/products/hiperclocks.html 14 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT ° ...

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