ICS8305 Integrated Circuit System, ICS8305 Datasheet - Page 9

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ICS8305

Manufacturer Part Number
ICS8305
Description
Manufacturer
Integrated Circuit System
Datasheet

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W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
8305AG
IRING THE
D
IFFERENTIAL
I
F
NPUT TO
IGURE
Single Ended Clock Input
2. S
A
A
PPLICATION
CCEPT
INGLE
www.icst.com/products/hiperclocks.html
E
C1
0.1u
S
NDED
V_REF
INGLE
DD
LVCMOS-
/2 is
S
L
IGNAL
OW
E
9
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
S
1K
D
R1
1K
R2
KEW
RIVING
VDD
L
TO
EVELS
, 1-
CLK
nCLK
D
-LVCMOS/LVTTL F
IFFERENTIAL
TO
-4, M
I
NPUT
ULTIPLEXED
DD
= 3.3V, V_REF should be 1.25V
ANOUT
D
ICS8305
IFFERENTIAL
REV. A JUNE 27, 2003
B
UFFER
/

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