wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 71

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

CLOCKING AND SAMPLE RATES
w
WM8961
MCLK
Figure 43 Clock Structure
SYSCLK
.
All internal clocks are derived from SYSCLK.
SYSCLK is either MCLK or MCLK/2
ADCDIV
ADC clock is set by ADCDIV (Master or Slave mode)
This is configured to output a clock of 256fs
DACDIV
DAC clock is set by DACDIV (Master or Slave mode)
This is configured to output a clock as close as possible to 3MHz
CLK_256K_DIV
This is a general clock divider which divides down the
SYSCLK (default is SYSCLK/48 = 256 kHz when
SYSCLK =12.288MHz operation)
BCLKDIV
BCLK rate is set by BCLKDIV in master mode.
Note that both ADC and DAC operate at the same
sample rate.
LRCLK_RATE
LRC is set by the LRCLK_RATE in master mode.
This is an integer division of the BCLK.
CLK_DCS_DIV
The DC Servo Clock is controlled by the CLK_DCS_DIV. This should be set to
provide a 1.5 MHz clock to the DC Servo.
DCLKDIV
Class D switching clock frequency is set by DCLKDIV and should be set to
operate the Class D function at a frequency of
384 kHz for optimum performance
TIMEOUT
A slow clock is used for volume update timeouts (when zero cross is enabled).
The timeout period is set by CLK_TO_DIV
.
Other Sample Rate Controls
.
SAMPLE_RATE[2:0] configures the ALC for a chosen sample rate.
DEEMPH[1:0] configures the de-emphasis filter for the chosen sample rate.
CLK_SYS_RATE[3:0] defines the relationship between the MCLK and the
sample rate
R8[5], CLK_SYS_ENA
R4[2], MCLKDIV
Clocks for the ADC and DAC, DSP core functions, the digital audio interface (AIF), the charge pump
and the class D outputs are all derived from the MCLK clock input. This is as show in Figure 43.
f/N
SYSCLK
CLK_DSP_ENA
R8[4],
CLK_256K_DIV[5:0]
ADCDIV[2:0]
BCLKDIV[3:0]
CLK_DCS_DIV[3:0]
DCLKDIV[2:0]
DACDIV[2:0]
R4[8:6],
R8[3:0],
R4[5:3],
R8[8:6],
R30[6:1],
f/N
f/N
R56[8:5],
f/N
f/N
f/N
divided by f/3 to give 128fs for the ADC
f/N
(*) In 384fs mode, ADCDIV should be
configured to give 384fs. This is then
LRCLK_RATE[8:0]
256fs(*)
DC Servo
R14[8:0],
f/2
f N
R23[0], TOEN
/
ADC_OSR
R23[5],
Class D Switching Clock
f/2 (*)
f/64
f/N
f/16
4 kHz
OUTPUTS
Charge pump
DAC
clock division
MASTER
TIMEOUT
CLOCK
MODE
CLK_TO_DIV[3:0]
PP, August 2009, Rev 3.1
Charge
Sequencer
Pump
R30[8,7],
Write
ADC
R7[6], MS
Pre-Production
Volume
Analog
Update
BCLK
LRC
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