wm9090 Wolfson Microelectronics plc, wm9090 Datasheet
wm9090
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wm9090 Summary of contents
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... DC offset correction to less than 1mV guarantees a pop/click-free headphone start up. WM9090 is controlled using a two-wire I2C interface. An integrated oscillator generates all internal clocks, removing the need to provide any external clock. WM9090 is available in a 2.53mm x 2.07mm 20-bump CSP package. BLOCK DIAGRAM IN1P IN1N VMID ...
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... WM9090 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ......................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 THERMAL PERFORMANCE ................................................................................. 7 ELECTRICAL CHARACTERISTICS ...................................................................... 8 TERMINOLOGY ........................................................................................................... 10 AUDIO SIGNAL PATHS DIAGRAM ..................................................................... 11 CONTROL INTERFACE TIMING ......................................................................... 12 DEVICE DESCRIPTION ....................................................................................... 13 INTRODUCTION .......................................................................................................... 13 INPUT SIGNAL PATH .................................................................................................. 14 LINE INPUTS ............................................................................................................................................ 15 INPUT PGA ENABLE ................................................................................................................................ 15 INPUT PGA CONFIGURATION ...
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... SOFTWARE RESET AND CHIP ID ............................................................................. 52 REGISTER MAP ................................................................................................... 53 REGISTER BITS BY ADDRESS .................................................................................. 55 APPLICATIONS INFORMATION ......................................................................... 71 RECOMMENDED EXTERNAL COMPONENTS ........................................................... 71 AUDIO INPUT PATHS ............................................................................................................................... 72 POWER SUPPLY DECOUPLING ............................................................................................................. 73 HEADPHONE OUTPUT PATH .................................................................................................................. 73 CLASS D SPEAKER CONNECTIONS ...................................................................................................... 74 PCB LAYOUT CONSIDERATIONS .............................................................................. 76 CLASS D LOUDSPEAKER CONNECTION .............................................................................................. 76 PACKAGE DIMENSIONS .................................................................................... 77 IMPORTANT NOTICE .......................................................................................... 78 ADDRESS: ................................................................................................................... 78 w WM9090 PP, January 2010, Rev 3.0 3 ...
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... WM9090 PIN CONFIGURATION 20-bump CSP package; Top View ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM9090ECS/R -40°C to +85°C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 20-ball W-CSP MSL1 (Pb-free, Tape and reel) Pre-Production PEAK SOLDERING TEMPERATURE 260°C PP, January 2010, Rev 3.0 ...
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... Charge pump positive rail decoupling pin Analogue supply Control interface clock Control interface data Mid-rail voltage decoupling pin Charge pump flyback capacitor pin Charge pump flyback capacitor pin Charge pump negative rail decoupling pin Left headphone output Right headphone output WM9090 DESCRIPTION PP, January 2010, Rev 3.0 5 ...
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... WM9090 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... Pre-Production THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM9090 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction ...
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... WM9090 ELECTRICAL CHARACTERISTICS Test Conditions SPKVDD = 3.6V, AVDD=1.8V, GND=0V, T PARAMETER Analogue Input Pins Maximum Full-Scale input signal level - IN1P/N and IN2P/N Input Resistance Input Capacitance Input Programmable Gain Amplifiers (PGAs) IN1A, IN1B, IN2A and IN2B Minimum Programmable Gain Maximum Programmable Gain Mute Attenuation ...
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... SPKVDD=4.2V, THD+N ≤ 1%, Speaker Boost = 12dB SPKVDD=3.7V, THD+N ≤ 1%, Speaker Boost = 12dB Normal mode Low power mode Normal mode Low power mode 1mA -1mA OH Speaker and Headphone WM9090 MIN TYP MAX UNIT - TBD mV 85 ...
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... WM9090 TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal ...
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... Pre-Production AUDIO SIGNAL PATHS DIAGRAM w WM9090 PP, January 2010, Rev 3.0 11 ...
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... WM9090 CONTROL INTERFACE TIMING START SCLK (input SDA Figure 2 Control Interface Timing Test Conditions SPKVDD = 3.6V, AVDD=1.8V, GND=0V, T PARAMETER SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDA, SCLK Rise Time ...
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... An integrated oscillator is provided to support all the WM9090 clocking requirements, including the Class D switching clock, Headphone Charge Pump and DC Servo control. The WM9090 is controlled via a standard 2-wire I2C interface, providing full software control of all features, together with device register readback. The interface provides support for I/O voltages up to 2.7V. An integrated Control Write Sequencer enables automatic scheduling of control sequences ...
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... The WM9090 supports two differential analogue input channels, configurable in a number of combinations: The inputs may be mixed together or independently routed to different combinations of output drivers. The WM9090 input signal paths and control registers are illustrated in Figure 3. Figure 3 Control Registers for Input Signal Path w • ...
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... Enabled (Note this is only required for single-ended input on the IN1N pin) IN2A_ENA IN2A Input PGA Enable Disabled 1 = Enabled 4 IN2B_ENA 0 IN2B Input PGA Enable 0 = Disabled 1 = Enabled (Note this is only required for single-ended input on the IN2N pin) WM9090 DESCRIPTION PP, January 2010, Rev 3.0 15 ...
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... WM9090 INPUT PGA CONFIGURATION The input PGAs can be configured in single-ended mode or differential mode, using the IN1_DIFF and IN2_DIFF register bits described in Table 2. In single-ended mode, an input pin is routed to each individual PGA. In differential mode, a pair of input pins is routed to PGA IN1A or IN2A. REGISTER ...
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... IN2_VU N/A Input PGA Volume Update Writing this bit will cause IN2A and IN2B input PGA volumes to be updated simultaneously IN2A_MUTE IN2A PGA Mute Un-Mute 1 = Mute WM9090 DESCRIPTION PP, January 2010, Rev 3.0 17 ...
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... WM9090 REGISTER ADDRESS R27 (1Bh) IN2 Line Input B Volume Table 3 Input PGA Volume Control w BIT LABEL DEFAULT 6 IN2A_ZC 0 IN2A PGA Zero Cross Control 0 = Change gain immediately 1 = Change gain on zero cross only IN2A_VOL IN2A Volume (differential mode) 2:0 011 [2:0] 000 = -6dB 001 = -3.5dB 010 = 0dB 011 = +3 ...
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... Pre-Production OUTPUT SIGNAL PATH The WM9090 output mixers provide a high degree of flexibility, allowing configurable operation of multiple signal paths through the device to a variety of analogue outputs. The outputs comprise a ground referenced headphone driver and Class D loudspeaker driver. See “Analogue Outputs” for further details of these outputs ...
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... WM9090 REGISTER ADDRESS (3) Table 4 Output Signal Paths Enable SPEAKER MIXER CONTROL The signal path configuration registers for the Speaker Mixer are described in Table 5. Each of the input PGAs IN1A, IN1B, IN2A and IN2B is independently selectable as an input to the Speaker Mixer. Care should be taken when enabling more than one path to a Speaker Mixer in order to avoid clipping ...
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... SPKOUTL_ZC 6 SPKOUTL_MUTE SPKOUTL_VOL [5:0] 5:0 39h (0dB) BIT LABEL DEFAULT 4 SPKMIXL_TO_SPKOU 1 TL WM9090 DESCRIPTION IN2B to SPKMIX volume control 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB DESCRIPTION Speaker Output PGA Volume Update Writing this bit will update the SPKOUTL volume. 0 Speaker Output PGA Zero Cross Control ...
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... WM9090 HEADPHONE MIXER CONTROL The Headphone Mixer configuration registers are described in Table 8 for the Left Channel (MIXOUTL) and Table 9 for the Right Channel (MIXOUTR). A subset of the available input PGAs IN1A, IN1B, IN2A and IN2B is selectable as an input to each of the Headphone Mixers, as illustrated in Figure 4 ...
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... BIT LABEL DEFAULT HPOUT1_VU 8 N/A HPOUT1L_ZC HPOUT1L_MUTE 0 HPOUT1L_VOL [5:0] 5:0 2Dh (-12dB) WM9090 DESCRIPTION IN1A to MIXOUTR volume control 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB IN1B to MIXOUTR volume control 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB IN2A to MIXOUTR volume control 00 = 0dB 01 = -6dB 10 = -9dB 11 = -12dB IN2B to MIXOUTR volume control ...
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... WM9090 REGISTER ADDRESS R29 (1Dh) Right Output Volume Table 10 Headphone Output PGA Control PGA GAIN SETTING Table 11 Output PGA Volume Range w BIT LABEL 8 HPOUT1_VU 7 HPOUT1R_ZC 6 HPOUT1R_MUTE 5:0 HPOUT1R_VOL [5:0] VOLUME (dB) PGA GAIN SETTING 0h -57 1h -56 2h -55 3h -54 4h -53 5h -52 6h -51 7h -50 8h -49 9h -48 ...
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... BIT LABEL DEFAULT 14 AGC_ENA 0 8 AGC_RAMP 0 AGC_MINGAIN [5:0] 5:0 00000 WM9090 DESCRIPTION AGC Enable 0 = Disabled 1 = Enabled AGC Ramp Control Selects how the AGC gain adjustment is applied 0 = Multiple gains steps per zero- cross 1 = Single gain step per zero-cross AGC Minimum Gain -57dB to +6dB in 1dB steps ...
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... WM9090 When the AGC applies signal attenuation triggered by the anti-clip threshold, the signal gain is reduced at a rate that is set by the AGC_CLIP_ATK register. When the anti-clip threshold is no longer met (due to the signal level reduction), then the AGC increases the signal gain at a rate set by the AGC_CLIP_DCY register ...
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... Note that, when the anti-clip and power limiting thresholds are both triggered concurrently, then the signal gain is reduced at the rate set by the AGC_CLIP_ATK register and is increased at the rate set by AGC_PWR_DCY. These fields are defined in Table 13 and Table 14 respectively. w WM9090 PP, January 2010, Rev 3.0 27 ...
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... WM9090 REGISTER ADDRESS R99 (63h) AGC Control 1 Table 14 AGC Power Limit Control w BIT LABEL DEFAULT 15 AGC_PWR_ENA 1 AGC_PWR_AVG 12 0 11:8 AGC_PWR_THR [2:0] 0000 6:4 AGC_PWR_ATK [2:0] 000 2:0 AGC_PWR_DCY [2:0] 000 Pre-Production DESCRIPTION Enable AGC Power Limit Mode 0 = Disabled 1 = Enabled AGC Power Measurement mode 0 = Peak power 1 = RMS power ...
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... Table 15 Speaker Boost Control w BIT LABEL DEFAULT 5:3 SPKOUTL_BOOST 000 [2:0] (1.0x) WM9090 DESCRIPTION Speaker Output Gain Boost 000 = 1.00x boost (+0dB) 001 = 1.19x boost (+1.5dB) 010 = 1.41x boost (+3.0dB) 011 = 1.68x boost (+4.5dB) 100 = 2.00x boost (+6.0dB) 101 = 2.37x boost (+7.5dB) 110 = 2.81x boost (+9.0dB) 111 = 3 ...
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... Figure 6 Zobel Network Components for HPOUTL and HPOUTR CLOCKING CONTROL The internal clocks for the WM9090 are derived from a common internal clock source, CLK_SYS. This clock is the reference for the Control Write Sequencer, Class D switching amplifier, DC servo control and other internal functions. ...
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... TOCLK Rate Divider (/ TOCLK Enable 0 = Disabled 1 = Enabled 0 TOCLK Rate Divider (/16 TOCLK Rate Multiplier TOCLK FREQ (Hz) PERIOD (ms) 0 1000 0 500 0 250 0 125 1 62.5 1 31.25 1 15.625 1 7.8125 128 PP, January 2010, Rev 3.0 WM9090 ...
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... The WM9090 is controlled by writing to registers through a 2-wire serial control interface. Readback is available for all registers, including Chip ID and power management status. The WM9090 is a slave device on the control interface; SCLK is a clock input, while SDA is a bi- directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM9090 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high ...
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... The terminology used in the following figures is detailed in Table 18. Note that multiple write and multiple read operations are supported using the auto-increment mode. This feature enables the host processor to access sequential blocks of the data in the WM9090 register map faster than is possible with single register operations. TERMINOLOGY ...
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... WM9090 Figure 10 Single Register Write to Specified Address Figure 11 Single Register Read from Specified Address Figure 12 Multiple Register Write to Specified Address using Auto-increment Figure 13 Multiple Register Read from Specified Address using Auto-increment Figure 14 Multiple Register Read from Last Address using Auto-increment w Pre-Production PP, January 2010, Rev 3 ...
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... Pre-Production CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM9090 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. Default sequences for Start-Up of each output driver and Shut-Down are provided (see “ ...
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... WM9090 REGISTER ADDRESS R70 (46h) Write Sequencer 0 R73 (49h) Write Sequencer 3 R74 (4Ah) Write Sequencer 4 R75 (4Bh) Write Sequencer 5 Table 19 Write Sequencer Control - Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write operations to data bits (or groups of bits) within the control registers. The Register fields associated with programming the Control Write Sequencer are described in Table 20 ...
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... Total time per step (including execution) WSEQ_DELAY = 62.5μs × Data to be written in this sequence step. When the data width is less than 8 bits, then one or more of the MSBs of WSEQ_DATA are ignored recommended that unused bits be set to 0. PP, January 2010, Rev 3.0 WM9090 37 ...
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... Control Register R1 [2:1] with the contents of WSEQ_DATA [1:0]. Figure 15 Control Write Sequencer Example DEFAULT SEQUENCES When the WM9090 is powered up, a number of Control Write Sequences are available through default settings in both RAM and ROM memory locations. The pre-programmed default settings comprise a Headphone Start-Up and a Generic Shut-Down sequence. ...
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... DC offset correction has not previously been run. 2. Generic Shut-Down - This sequence shuts down all of the WM9090 output drivers, DC Servo and charge pump circuits. Specific details of these sequences are provided below. Note that the timings noted are typical values only ...
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... WM9090 Generic Shut-Down The Generic Shut-Down sequence can be initiated by writing 0110h to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence defined in Table 22. This sequence takes approximately 2.8ms to run. WSEQ REGISTER WIDTH INDEX ADDRESS ...
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... INPUT VMID CLAMPS The analogue inputs are biased to VMID in normal operation. In order to avoid audible pops caused by enabling the inputs, the WM9090 can clamp the input pins to VMID when the relevant input stage is disabled. This allows pre-charging of the input AC coupling capacitors during power-up. ...
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... WM9090 Step 1 Step 2 Table 25 Headphone Output Disable Sequence The register bits relating to pop suppression control are defined in Table 26. REGISTER ADDRESS R1 (01h) Power Management (1) R96 (60h) Analogue SEQUENCE HEADPHONE DISABLE HPOUT1L_RMV_SHORT = 0 HPOUT1L_DLY = 0 HPOUT1L_OUTP = 0 HPOUT1R_RMV_SHORT = 0 HPOUT1R_DLY = 0 HPOUT1R_OUTP = 0 HPOUT1L_ENA = 0 HPOUT1R_ENA = 0 BIT LABEL 9 HPOUT1L_ENA ...
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... ADDRESS Table 26 Pop Suppression Control w BIT LABEL DEFAULT HPOUT1R_OUTP HPOUT1R_DLY 0 WM9090 DESCRIPTION Enables HPOUT1R output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. Enables HPOUT1R intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should ...
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... The Charge Pump mode of operation is selected automatically according to the HPOUT1L_VOL and HPOUT1R_VOL register settings. Under the recommended usage conditions of the WM9090, the Charge Pump will be enabled by running the default headphone Start-Up sequence as described in the “Control Write Sequencer” section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user does not need to write to the CP_ENA bit ...
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... Pre-Production DC SERVO The WM9090 provides a DC servo circuit on the headphone outputs HPOUTL and HPOUTR in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs remains within 1mV of ground. Removal of the DC offset is important because any deviation from GND at the output pin will cause current to flow through the load under quiescent conditions, resulting in increased power consumption ...
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... WM9090 REGISTER ADDRESS R84 (54h) DC Servo 0 R87 (57h) DC Servo 3 R88 (58h) DC Servo Readback 0 w BIT LABEL DEFAULT 5 DCS_TRIG_START 0 UP_1 4 DCS_TRIG_START 0 UP_0 DCS_TRIG_DAC_W 3 0 R_1 2 DCS_TRIG_DAC_W 0 R_0 1 DCS_ENA_CHAN_1 0 DCS_ENA_CHAN_0 0 0 DCS_DAC_WR_VA 15:8 0000 0000 L1 [7:0] DCS_DAC_WR_VA 7:0 0000 0000 L0 [7:0] 9:8 DCS_CAL_COMPL 00 ETE [1:0] Pre-Production DESCRIPTION Writing 1 to this bit selects Start Servo mode for HPOUT1L ...
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... DCS_STARTUP_C 00 OMPLETE [1:0] BIT LABEL DEFAULT 13 DCS_TRIG_SINGLE 0 _1 WM9090 DESCRIPTION DC Servo DAC Write status 00 = DAC Write DC Servo mode not completed DAC Write DC Servo mode complete on HPOUT1R only DAC Write DC Servo mode complete on HPOUT1L only DAC Write DC Servo mode complete on HPOUT1L and HPOUT1R. ...
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... WM9090 REGISTER ADDRESS R85 (55h) DC Servo 1 Table 29 DC Servo Active Modes DC SERVO READBACK The current DC offset value for each Headphone output channel can be read from Registers R89 and R90, as described in Table 30. Note that these values may form the basis of settings that are subsequently used by the DC Servo in DAC Write mode ...
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... VMID_RES register should be updated after start-up to select another resistor value. The analogue circuits in the WM9090 require a bias current. The normal bias current is enabled by setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also. ...
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... WM9090 POWER MANAGEMENT The WM9090 provides control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise important to enable or disable functions in the correct order. See “Power Sequences and Pop Suppression Control” ...
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... WSEQ_ENA 0 15 CP_ENA 0 1 DCS_ENA_CHAN 0 _1 DCS_ENA_CHAN WM9090 DESCRIPTION IN2B Input PGA Enable 0 = Disabled 1 = Enabled (Note this is only required for single- ended input on the IN2N pin) Speaker PGA Enable 0 = Disabled 1 = Enabled MIXOUTL Headphone Mixer Enable 0 = Disabled 1 = Enabled MIXOUTR Headphone Mixer Enable ...
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... The temperature status can be polled at any time by reading the TSHUT register bit. The temperature sensor can be configured to automatically disable the audio outputs of the WM9090 in response to an over-temperature condition (approximately 150ºC). ...
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... Pre-Production REGISTER MAP w WM9090 PP, January 2010, Rev 3.0 53 ...
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... WM9090 w Pre-Production PP, January 2010, Rev 3.0 54 ...
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... Over temperature 1 Thermal sensor enable 0 = Disabled 1 = Enabled 1 Thermal shutdown control (Causes audio outputs to be disabled if an overtemperature occurs. The thermal sensor must also be enabled Disabled 1 = Enabled IN1A Input PGA Enable Disabled 1 = Enabled WM9090 REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 55 ...
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... WM9090 REGISTER BIT LABEL ADDRESS 6 IN1B_ENA 5 IN2A_ENA 4 IN2B_ENA Register 02h Power Management (2) REGISTER BIT LABEL ADDRESS R3 (03h) 14 AGC_ENA Power Managemen t (3) 8 SPKLVOL_EN A 5 MIXOUTL_EN A 4 MIXOUTR_EN A 3 SPKMIX_ENA Register 03h Power Management (3) REGISTER BIT LABEL ADDRESS R6 (06h) 15 TOCLK_RATE Clocking 1 14 TOCLK_ENA ...
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... IN1A Volume (single-ended mode) 000 = 0dB 001 = +2.5dB 010 = +6dB 011 = +9.5dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +24dB WM9090 REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 57 ...
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... WM9090 REGISTER BIT LABEL ADDRESS R25 (19h) 8 IN1_VU IN1 Line Input B Volume 7 IN1B_MUTE 6 IN1B_ZC 2:0 IN1B_VOL [2:0] Register 19h IN1 Line Input B Volume REGISTER BIT LABEL ADDRESS R26 (1Ah) 8 IN2_VU IN2 Line Input A Volume 7 IN2A_MUTE 6 IN2A_ZC 2:0 IN2A_VOL [2:0] w DEFAULT DESCRIPTION 0 IN1 Volume Update Writing this bit will cause IN1A and IN1B input ...
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... Writing this bit will update HPOUT1LVOL and HPOUT1RVOL volumes simultaneously. 0 Left Headphone Output PGA Zero Cross Control 0 = Change gain immediately 1 = Change gain on zero cross only Left Headphone Output PGA Mute Un-mute WM9090 REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 59 ...
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... WM9090 REGISTER BIT LABEL ADDRESS 5:0 HPOUT1L_VO L [5:0] Register 1Ch Left Output Volume REGISTER BIT LABEL ADDRESS R29 (1Dh) 8 HPOUT1_VU Right Output Volume 7 HPOUT1R_ZC 6 HPOUT1R_MU TE 5:0 HPOUT1R_VO L [5:0] Register 1Dh Right Output Volume REGISTER BIT LABEL ADDRESS R34 (22h) 8 SPKMIX_MUT SPKMIXL E Attenuation 7:6 IN1A_SPKMIX _VOL [1:0] 5:4 IN1B_SPKMIX ...
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... Change gain on zero cross only Speaker Output PGA Mute Un-mute 1 = Mute 11_1001 Speaker Output PGA Volume -57dB to +6dB in 1dB steps DEFAULT DESCRIPTION 0 IN1A to MIXOUTL enable 0 = Disabled 1 = Enabled 0 IN2A to MIXOUTL enable 0 = Disabled 1 = Enabled WM9090 REFER TO REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 61 ...
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... WM9090 REGISTER BIT LABEL ADDRESS R46 (2Eh) 6 IN1A_TO_MIX Output OUTR Mixer2 4 IN1B_TO_MIX OUTR 2 IN2A_TO_MIX OUTR 0 IN2B_TO_MIX OUTR Register 2Eh Output Mixer2 REGISTER BIT LABEL ADDRESS R47 (2Fh) 8 MIXOUTL_MU Output TE Mixer3 7:6 IN1A_MIXOUT L_VOL [1:0] 3:2 IN2A_MIXOUT L_VOL [1:0] Register 2Fh Output Mixer3 REGISTER BIT LABEL ...
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... Enable VMID master bias current source 0 = Disabled 1 = Enabled DEFAULT DESCRIPTION 0 Write Sequencer Enable Disabled 1 = Enabled 0000 Sequence Write Index. This is the memory location to which any updates to R71 and R72 will be copied RAM addresses WM9090 REFER TO REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 63 ...
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... WM9090 REGISTER BIT LABEL ADDRESS R71 (47h) 14:12 WSEQ_DATA_ Write WIDTH [2:0] Sequencer 1 11:8 WSEQ_DATA_ START [3:0] 7:0 WSEQ_ADDR [7:0] Register 47h Write Sequencer 1 REGISTER BIT LABEL ADDRESS R72 (48h) 14 WSEQ_EOS Write Sequencer 2 11:8 WSEQ_DELAY [3:0] 7:0 WSEQ_DATA [7:0] Register 48h Write Sequencer 2 REGISTER BIT LABEL ADDRESS R73 (49h) 9 WSEQ_ABOR Write ...
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... Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1L. In readback, a value of 1 indicates that the DC Servo DAC Write correction is in progress. 0 Writing 1 to this bit selects DAC Write DC Servo mode for HPOUT1R. WM9090 REFER TO REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 65 ...
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... WM9090 REGISTER BIT LABEL ADDRESS 1 DCS_ENA_CH AN_1 0 DCS_ENA_CH AN_0 Register 54h DC Servo 0 REGISTER BIT LABEL ADDRESS R85 (55h) 11:5 DCS_SERIES_ DC Servo 1 NO_01 [6:0] 3:0 DCS_TIMER_P ERIOD_01 [3:0] Register 55h DC Servo 1 REGISTER BIT LABEL ADDRESS R87 (57h) 15:8 DCS_DAC_W DC Servo 3 R_VAL_1 [7:0] 7:0 DCS_DAC_W R_VAL_0 [7:0] Register 57h DC Servo 3 REGISTER ...
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... Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HPOUT1L_ENA. WM9090 REFER TO REFER TO REFER TO REFER TO PP, January 2010, Rev 3.0 ...
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... WM9090 REGISTER BIT LABEL ADDRESS 3 HPOUT1R_RM V_SHORT 2 HPOUT1R_OU TP 1 HPOUT1R_DL Y Register 60h Analogue HP 0 REGISTER BIT LABEL ADDRESS R98 (62h) 15 AGC_CLIP_EN A AGC Control 0 11:8 AGC_CLIP_TH R [3:0] 6:4 AGC_CLIP_AT K [2:0] w DEFAULT DESCRIPTION 0 Removes HPOUT1R short 0 = HPOUT1R short enabled 1 = HPOUT1R short removed For pop-free operation, this bit should be set the final step in the HPOUTR Enable sequence ...
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... Sets the rate of AGC gain reduction when power limiting is applied 000 = 120ms/6dB 001 = 480ms/6dB 010 = 840ms/6dB 011 = 1200ms/6dB 100 = 1680ms/6dB 101 = 2040ms/6dB 110 = 2760ms/6dB 111 = 4080ms/6dB 000 AGC Power Limiting Decay Rate Sets the rate of AGC gain increments after a period of WM9090 REFER TO REFER TO PP, January 2010, Rev 3.0 69 ...
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... WM9090 REGISTER BIT LABEL ADDRESS Register 63h AGC Control 1 REGISTER BIT LABEL ADDRESS R100 (64h) 8 AGC_RAMP AGC Control 2 5:0 AGC_MINGAIN [5:0] Register 64h AGC Control 2 w DEFAULT DESCRIPTION power limiting 000 = 1080ms/6dB 001 = 1200ms/6dB 010 = 1320ms/6dB 011 = 1680ms/6dB 100 = 2040ms/6dB 101 = 2760ms/6dB 110 = 4080ms/6dB ...
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... APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 17 below provides a summary of recommended external components for WM9090. Note that the diagram does not include any components that are specific to the end application e.g. they do not include filtering on the speaker outputs (assume filterless class D operation), RF decoupling filtering for pins which connect to the external world i ...
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... WM9090 AUDIO INPUT PATHS The WM9090 provides 4 analogue audio inputs. Each of these inputs is referenced to the internal DC reference, VMID blocking capacitor is required for each input pin used in the target application. The choice of capacitor is determined by the filter that is formed between that capacitor and the input impedance of the input pin ...
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... All decoupling capacitors should be placed as close as possible to the WM9090 device. The connection between GND, the AVDD decoupling capacitor and the main system ground should be made at a single point as close as possible to the GND ball of the WM9090. The VMID capacitor is not, technically, a decoupling capacitor. However, it does serve a similar purpose in filtering noise on the VMID reference ...
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... WM9090 CLASS D SPEAKER CONNECTIONS The WM9090 incorporates a Class D speaker driver. As the Class D output is a pulse width modulated (PWM) signal, the choice of speakers and tracking of signals is critical for ensuring good performance and reducing EMI in this mode. The efficiency of the speaker drivers is affected by the series resistance between the WM9090 and the speaker (e ...
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... Class D switching and doing, to prevent speaker damage. The Class D outputs of the WM9090 operate at much higher frequencies than is recommended for most speakers and it must be ensured that the cut-off frequency is low enough to protect the speaker. ...
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... Further reduction in EMI can be achieved using PCB ground (or VDD) planes and also by using passive LC components to filter the Class D switching waveform. When passive filtering is used, low ESR components should be chosen in order to minimise the series resistance between the WM9090 and the speaker, maximising the power efficiency. ...
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... FOLLOWS JEDEC DESIGN GUIDE MO-211-C. w 2.070 0.7mm BODY, 0.50 mm BALL PITCH X X DETAIL CORNER DETAIL 2 MAX NOTE 0.785 0.269 0.411 2.560 2.100 5 0.105 DM073 0.10 Z 0.10 Z TOP VIEW f1 SOLDER BALL f2 h DETAIL 1 PP, January 2010, Rev 3.0 WM9090 E 77 ...
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... WM9090 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...