wm8595 Wolfson Microelectronics plc, wm8595 Datasheet
wm8595
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wm8595 Summary of contents
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... The WM8595 supports up to 2Vrms analogue inputs, 2Vrms outputs, with sample rates from 32kHz to 192kHz on the DACs, and 32kHz to 96kHz on the ADC. The WM8595 is controlled via a serial interface with support for 2-wire and 3-wire control with full readback. Control of mute, emergency shutdown and reset can also be achieved by pin selection ...
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... WM8595 BLOCK DIAGRAM w Production Data PD, Rev 4.1, April 2010 2 ...
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... DIGITAL ROUTING CONTROL ................................................................................... 40 POP AND CLICK PERFORMANCE ............................................................................ 46 GLOBAL ENABLE CONTROL ..................................................................................... 48 EMERGENCY POWER DOWN ................................................................................... 49 REGISTER MAP ................................................................................................... 50 DIGITAL FILTER CHARACTERISTICS ............................................................... 74 APPLICATIONS INFORMATION ......................................................................... 78 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 78 RECOMMENDED ANALOGUE LOW PASS FILTER .................................................. 79 RELEVANT APPLICATION NOTES ............................................................................ 79 PACKAGE DIMENSIONS .................................................................................... 80 IMPORTANT NOTICE .......................................................................................... 81 ADDRESS ................................................................................................................... 81 w TABLE OF CONTENTS WM8595 PD, Rev 4.1, April 2010 3 ...
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... WM8595 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8595GEFL/V -40°C to +85°C WM8595GEFL/RV -40°C to +85°C Note: Reel quantity = 2200 w PACKAGE MOISTURE SENSITIVITY 48-lead QFN (Pb-free) 48-lead QFN (Pb-free, tape and reel) Production Data PACKAGE BODY LEVEL TEMPERATURE o MSL3 260 ...
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... Serial Data output for 3-wire readback Digital Input 3-wire serial control interface latch Software mode: serial control interface clock signal Digital Input Digital Input Software mode: bi-directional serial control interface data signal WM8595 DESCRIPTION PD, Rev 4.1, April 2010 5 ...
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... WM8595 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... I AVDD1 Quiescent I AVDD2 I DVDD fs=48kHz, 256fs I AVDD1 Quiescent I AVDD2 I DVDD fs=96kHz, 256fs I AVDD1 Quiescent I AVDD2 I DVDD fs=192kHz, 256fs I AVDD1 Quiescent I AVDD2 I DVDD fs=48kHz, 256fs I AVDD1 Quiescent I AVDD2 WM8595 MIN TYP MAX 2.97 3.3 3.6 2.97 3.3 3.6 8.1 9 9.9 0 -40 +85 MIN TYP MAX 8.6 9.2 0.01 5.5 6.5 2.0 9.5 7.0 2.0 10.0 7.0 2.0 17.0 20.0 11.0 PD, Rev 4.1, April 2010 UNIT V V ...
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... WM8595 ELECTRICAL CHARACTERISTICS Test Conditions AVDD2=9V, AVDD1=DVDD=3.3V, AGND1=AGND2=0V, DGND=0V, T PARAMETER Digital logic levels Input low level Input high level Output low level Output high level Digital input leakage current Digital input capacitance Analogue Reference Levels ADC Midrail Voltage ADC Buffered Positive ...
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... PSRR 1kHz, 100mVpp 20Hz to 20kHz, 100mVpp 1kHz signal, ADC fs=48kHz, DAC fs=44.1kHz 20kHz signal, ADC fs=48kHz, DAC fs=44.1kHz 1kHz signal, ADC fs=48kHz, DAC fs=44.1kHz 20kHz signal, ADC fs=48kHz, DAC fs=44.1kHz WM8595 MIN TYP MAX -80 -70 -78 110 0.1 0. ...
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... WM8595 TERMINOLOGY 1. Signal-to-noise ratio (dBFS) – SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dBFS) – DNR is a measure of the difference in level between the highest and lowest components of a signal ...
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... Table 2 RESET ¯ ¯ ¯ ¯ ¯ ¯ Timing Requirements + SYMBOL MIN TYP t 27 MCLKY 40: + SYMBOL MIN TYP T 10 RESET WM8595 MAX UNIT 120 ns 60:40 % 200 MAX UNIT ns PD, Rev 4.1, April 2010 11 ...
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... WM8595 DIGITAL AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Slave Mode Digital Audio Data Timing Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high ...
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... DACDAT (input) setup time to BCLK rising edge DACDAT (input) hold time to BCLK rising edge Table 4 Master Mode Audio Interface Timing w = +25˚C, Slave Mode 48kHz, MCLK = 256fs, A SYMBOL MIN TYP DDA t 22 DST t 25 DHT WM8595 MAX UNIT PD, Rev 4.1, April 2010 13 ...
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... WM8595 CONTROL INTERFACE TIMING – 2-WIRE MODE Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, T 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK pulse cycle time SCLK duty cycle ...
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... Table 6 Control Interface Timing – 3-Wire Serial Control Mode w = +25˚C, Slave Mode 48kHz, MCLK = 256fs, A SYMBOL MIN TYP t 80 SCS t 160 SCY 40/ DSU t 40 DHO CSH t 40 CSS1 t 40 CSS2 WM8595 MAX UNIT ns ns 60/ PD, Rev 4.1, April 2010 15 ...
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... WM8595 POWER ON RESET (POR) Figure 1 Power Supply Timing Requirements Test Conditions DVDD = 3.3V, AVDD1 = 3.3V, AVDD2 = 9V DGND = AGND1 = AGND2 = 0V, T AVDD1 = DVDD = 3.63V, AVDD1 max max AVDD2 = 9.9V, AVDD2 = 8.1V max min PARAMETER SYMBOL Power Supply Input Timing Information VDD level to POR defined V pord (DVDD rising) ...
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... DEVICE DESCRIPTION INTRODUCTION The WM8595 is a high performance multi-channel audio CODEC with 2Vrms line level inputs and outputs and flexible digital input / output switching. The device comprises a 24-bit stereo ADC, two 24-bit stereo DACs with independent sampling rates and digital volume control, two stereo PGAs in the output path, a flexible digital audio interface multiplexer, a flexible analogue input multiplexer ...
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... SDA low for one SCLK pulse. The controller then sends a second byte of control data (B15 to B8, i.e. the first 8 bits of register data), and the WM8595 acknowledges again by pulling SDA low for one SCLK pulse. Finally, the controller sends a third byte of control data (B7 to B0, i.e. the final 8 bits of register data), and the WM8595 acknowledges again by pulling SDA low for one SCLK pulse ...
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... At this point the controller will issue a repeated start condition and resend the device address along with a read bit. The WM8595 will acknowledge this and the WM8595 will become a slave transmitter. The WM8595 will place the data from the indexed register onto SDA MSB first. When the controller receives the first byte of data, it acknowledges it ...
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... R/W bit is high. The data can then be read by writing to the appropriate register address, to which the device will respond with data. Figure 12 3-Wire Serial Interface Readback Protocol REGISTER RESET Any write to register R0 (00h) will reset the WM8595. All register bits are reset to their default values. w Production Data ¯ ¯ is use to latch PD, Rev 4 ...
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... Reading from register R0 returns the device ID. Reading from register R1 returns the device revision number. REGISTER ADDRESS R0 DEVICE_ID 00h R1 REVISION 01h Table 10 Device ID and Revision Number DIGITAL AUDIO DATA FORMATS The WM8595 supports a range of common audio interface formats: 2 • • Left Justified (LJ) • Right Justified (RJ) • DSP Mode A • ...
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... Figure 13 I2S Mode Timing LEFT JUSTIFIED (LJ) MODE In LJ mode, the MSB of the input data is sampled by the WM8595 on the first rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the same falling edge of bit clock as left/right clock and may be sampled on the next rising edge of bit clock. Left/right clock is high during the left channel audio data samples and low during the right channel audio data samples ...
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... Channel 1 right data then follows. The MSB of output data changes on the first falling edge of bit clock following a left/right clock transition and may be sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel data. Figure 16 DSP Mode A Timing w WM8595 PD, Rev 4.1, April 2010 23 ...
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... Interface timing is such that the input data and left/right clock are sampled on the rising edge of the interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the appropriate bit clock and left/right clock polarity bits, the WM8595 ADC and DACs can sample data on the opposite clock edges. ...
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... Right Justified mode) 4 ADC_BCP 0 ADC BCLK Polarity 0 = ADCBCLK not inverted - data latched on rising edge of BCLK 1 = ADCBCLK inverted - data latched on falling edge of BCLK 5 ADC_LRP 0 ADC LRCLK Polarity 0 = ADCLRCLK not inverted 1 = ADCLRCLK inverted WM8595 DESCRIPTION PD, Rev 4.1, April 2010 25 ...
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... WM8595 DIGITAL AUDIO INTERFACE Digital audio data is transferred to and from the WM8595 via the digital audio interface. The DACs have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate in both master or slave mode The ADC has independent master clock, bit clock and left/right frame clock in addition to its data output, and can operate in both master and slave modes ...
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... DAC2_ 000 011 = 256fs SR[2:0] 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs 2:0 ADC_ 000 ADC MCLK:LRCLK Ratio SR[2:0] 000 = Auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved WM8595 DESCRIPTION PD, Rev 4.1, April 2010 27 ...
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... WM8595. In slave clocking mode the WM8595 has a master detection circuit that automatically determines the relationship between the master clock frequency (ADCMCLK, DACMCLK1, DACMCLK2) and the sampling rate (ADCLRCLK, DACLRCLK1, DACLRCLK2), to within +/- 32 system clock periods ...
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... Production Data DAC FEATURES The WM8595 includes two 24-bit DACs with independent clocks and independent data inputs. The DACs include digital volume control with zero cross and soft mute, de-emphasis support, and the capability to select the output channels to be stereo or a range of mono options. The DACs are enabled by writing to DAC1_EN and DAC2_EN ...
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... WM8595 REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 17 DAC Digital Volume Control SOFTMUTE A soft mute can be applied to DAC1 and DAC2 independently. REGISTER ADDRESS R2 DAC1_CTRL1 02h R7 DAC2_CTRL1 07h Table 18 DAC Softmute Control 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 Figure 18 Application and Release of DAC Soft Mute Figure 18 shows the applications and release of DAC soft mute whilst a full amplitude sinusoid is being played at 48kHz sampling rate ...
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... R2 = 0x0001 & 0x0001 R3 = 0x0023 & 0x0023 R4 = 0x0045 & 0x0045 R5 = 0x0067 & R10 = 0x0067 R6 = 0x0089 & R11 = 0x0089 BIT LABEL DEFAULT 1 DAC2_ 0 DAC2 Configuration Control COPY_ 0 = DAC2 settings independent of DAC1 DAC1 1 = DAC2 settings are the same as DAC1 WM8595 DESCRIPTION DESCRIPTION DESCRIPTION PD, Rev 4.1, April 2010 31 ...
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... WM8595 ANALOGUE OUTPUT VOLUME CONTROL ANALOGUE VOLUME CONTROL Each analogue output includes analogue volume control. Volume changes can be applied to each output immediately as they are written. Alternatively, all volume changes can be written, and then all volume changes can be applied simultaneously using the volume update feature. ...
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... If the volume ramp function is not required when increasing or decreasing volume, this block can be bypassed by setting ATTACK_BYPASS or DECAY_BYPASS to 1. Figure 19 shows the effect of these register settings: Figure 19 ATTACK_BYPASS and DECAY_BYPASS Functionality w DIVIDE 44 88 176.4 32 192 32 WM8595 PGA RAMP RATE (ms/dB) 0.50 0.36 0.33 0.36 0.33 0.36 0.33 PD, Rev 4.1, April 2010 33 ...
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... WM8595 Note: When ATTACK_BYPASS=1 or DECAY_BYPASS= recommended that the zero cross function for the PGA is used to eliminate click noise when changing volume settings. REGISTER ADDRESS R25 PGA_CTRL1 19h R27 ADD_CTRL1 1Bh R36 PGA_CTRL3 24h Table 24 Analogue Volume Ramp Control w BIT LABEL ...
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... Mute all PGAs 1 PGA1L_ 1 Individual PGA Mute Control MUTE 0 = Unmute PGA 2 PGA1R_ Mute PGA MUTE 3 PGA2L_ 1 MUTE 4 PGA2R_ 1 MUTE BIT LABEL DEFAULT 0 PGA1L_ 0 PGA Enable Controls PGA disabled 1 = PGA enabled 1 PGA1R_ EN 2 PGA2L_ EN 3 PGA2R_ EN WM8595 DESCRIPTION DESCRIPTION PD, Rev 4.1, April 2010 35 ...
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... WM8595 ADC FEATURES The WM8595 features a stereo 24-bit sigma-delta ADC, digital volume control with zero cross, a selectable high pass filter to remove DC offsets, and support for both master and slave clocking modes. REGISTER ADDRESS R13 ADC_CTRL1 0Dh Table 27 ADC Enable Control ADC INPUT SELECTOR CONTROL The ADC input switch can be configured to allow any combination of two inputs to be input to the ADC ...
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... ADC Amplifier Gain Control _VOL[1: 0dB 01 = +3dB 10 = +6dB 11 = +12dB 10 ADC_ 0 ADC Input Switch Control SWITCH_ 0 = ADC input switches open ADC input switches closed 6 ADCL_ 0 ADC Input Amplifier Enable Controls AMP_EN 0 = Amplifier disabled 1 = Amplifier enabled 7 ADCR_ 0 AMP_EN WM8595 DESCRIPTION PD, Rev 4.1, April 2010 37 ...
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... WM8595 DIGITAL VOLUME CONTROL The ADC digital volume can be adjusted between +30dB and -97dB in 0.5dB steps. Left and right channels can be controlled independently. Volume changes can be applied immediately to each channel, or volume changes can be written to both channels before writing to an update bit in order to change the volume in both channels simultaneously ...
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... Production Data CHANNEL SWAP AND INVERSION The WM8595 ADC input channels can be inverted and swapped in a number of ways to provide maximum flexibility of input path to the ADC. The default configuration provides stereo output data with the left and right channel data in the left and right channels possible to swap the left and right channels, invert them independently, or select the same data from both channels ...
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... The default configuration of the clocking is as shown in Figure 22 below expected that this configuration will satisfy the majority of the use cases for the WM8595, but if it doesn’ possible to route the signals differently. See the following pages for details of this setup. ...
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... Reserved 6:4 WORD 001 BCLK2 and LRCLK2 Pins Function Select CLK2_ 000 = Output BCLK1 and LRCLK1 SEL[2:0] 001 = Inputs to WM8595 010 to 110 = Reserved 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) WM8595 The BCLK1 and DESCRIPTION The BCLK2 and DESCRIPTION PD, Rev 4 ...
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... WM8595 ADC AUDIO INTERFACE CLOCK CONFIGURATION The WM8595 ADC has an independent audio interface which can be configured to select the required signals from any of the digital audio ports. The audio interface is not restricted to take each signal from the same digital audio port, although the BCLK and LRCLK signals are selected together. ...
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... Production Data DAC1 AND DAC2 AUDIO INTERFACE CLOCK CONFIGURATION Both DACs on the WM8595 have independent audio interfaces which can be configured to select the required signals from any of the digital audio ports. The audio interfaces are not restricted to take each signal from the same digital audio ports, although the BCLK and LRCLK signals are selected together ...
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... Source ADC Data Output BIT LABEL DEFAULT 3:1 GPIO2_ 000 GPIO2 Pin Function Select SEL[2:0] 000 = Source DACDAT1 001 = Source DACDAT2 010 = Source ADCDAT 011 to 100 = Reserved 101 = Source GPIO1 110 = Input to WM8595 111 = Source ADC Data Output Production Data DESCRIPTION DESCRIPTION PD, Rev 4.1, April 2010 44 ...
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... LABEL DEFAULT 10 PORT1_ 0 Update UPD 0 = Latch corresponding settings into Register Map but do not update 1 = Latch corresponding settings into 10 PORT2_ Register Map and update all simultaneously UPD 10 DAC1_ UPD 10 DAC2_ UPD 10 ADC_ UPD 10 GPIO1_ UPD 10 GPIO2_ UPD WM8595 DESCRIPTION PD, Rev 4.1, April 2010 45 ...
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... WM8595 POP AND CLICK PERFORMANCE The WM8595 includes a number of features designed to minimise pops and clicks in various phases of operation including power up, power down, changing analogue paths and starting/stopping clocks. In order to ensure optimum performance, the following sequences should be followed. POWERUP SEQUENCE ...
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... Switch outputs to use fast bias instead of master bias: • POBCTRL=1 Power down all WM8595 functions (ADC, DACs, PGAs etc.). The outputs are muted so the write order is not important. Power down VMID to allow the analogue outputs to ramp gently to ground in a pop-free manner. ...
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... R35 BIAS 23h Table 39 Bias Control GLOBAL ENABLE CONTROL The WM8595 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. A global enable control bit enables the ADC, DAC and analogue paths. REGISTER ADDRESS R12 ...
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... This may be useful in a system where there is no guarantee the power supplies will be available long enough to complete the recommended power down sequence using software writes. When the SHUTDOWN If the WM8595 is still receiving clocks, the outputs will be softmuted. If the clocks have stopped, the outputs will be muted immediately. Figure 23 shows the operation of SHUTDOWN on the outputs of the device: ...
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... DEVICE_ID[15:8] SW_RST DEVICE_ID[7:0] SW_RST N/A = Not Applicable (no function implemented) Description N/A N/A N REVNUM[7:0] N/A N/A N N/A = Not Applicable (no function implemented) Description WM8595 N/A N/A N N/A N/A N PD, Rev 4.1, April 2010 51 ...
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... WM8595 R2 (02h) – DAC Control Register 1 (DAC1_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC1_ DAC1_ZCEN DEEMPH Write Default 1 0 Function DAC1_FMT[1:0] DAC1 Audio Interface Format 00 = Right Justified 01 = Left Justified DSP DAC1 Audio Interface Word Length ...
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... N/A N/A N N/A = Not Applicable (no function implemented) Description N/A N/A N DAC1L_VOL[7: N/A = Not Applicable (no function implemented) Description WM8595 N/A N/A N DAC1_SR[2: DAC1L_VU N/A N PD, Rev 4.1, April 2010 ...
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... WM8595 R6 (06h) – DAC1R Digital Volume Control Register (DAC1R_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function DAC1R_VOL[7:0] DAC1R Digital Volume 0000 0000 = -100dB 0000 0001 = -99.5dB 0000 0010 = -99dB …0.5dB steps 1100 1000 = 0dB … ...
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... Mono (Right data to Left DAC2 Digital Monomix, (L+R)/2 Figure 30 R7 – DAC2 Control Register DAC2_OP_MUX[1:0] N/A N DAC2_LRP DAC2_BCP DAC2_WL[1: Description WM8595 10 9 DAC2_MUTE DAC2_EN DAC2_FMT[1: N/A = Not Applicable (no function implemented) PD, Rev 4.1, April 2010 ...
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... WM8595 R8 (08h) – DAC2 Control Register 2 (DAC2_CTRL2) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function DAC2_SR[2:0] DAC2 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs Figure 31 R8 – ...
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... DAC2R_VOL[7: N/A = Not Applicable (no function implemented) Description N/A N/A N N/A N/A N N/A = Not Applicable (no function implemented) Description WM8595 DAC2R_VU N/A N N/A N/A N DAC2_ GLOBAL_EN COPY_DAC1 ...
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... WM8595 R13 (0Dh) – ADC Control Register 1 (ADC_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADC_ ADC_EN LRSWAP Write Default 0 0 Function ADC_FMT[1:0] ADC Audio Interface Format 00 = Right Justified 01 = Left Justified DSP ADC Audio Interface Word Length ...
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... Bit # 7 6 Read 0 0 Write N/A N/A Default 0 0 Function ADC Master Mode Select ADC_MSTR 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8595 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8595 Figure 37 R15 – ADC Control Register N/A N/A N ...
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... WM8595 R16 (10h) – Left ADC Digital Volume Control Register (ADCL_VOL) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read Write Default 1 1 Function ADCL_VOL[7:0] Left ADC Digital Volume 0000 0000 = Digital mute 0000 0001 = -97dB 0000 0010 = -96.5dB …0.5dB steps 1100 0011 = 0dB … ...
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... N/A N/A N PGA2L_VOL[7: N/A = Not Applicable (no function implemented N/A N/A N PGA2R_VOL[7: N/A = Not Applicable (no function implemented) WM8595 N/A N/A PGA1L_VU N/A N/A PGA1R_VU ...
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... WM8595 Function PGA1L_VOL[7:0] Input PGA Volume PGA1R_VOL[7:0] 0000 0000 = +6dB PGA2L_VOL[7:0] 0000 0001 = +5.5dB …0.5dB steps PGA2R_VOL[7:0] 00001100 = 0dB … 1001 1110 = -73.5dB 1001 1111 = PGA Mute Input PGA Volume Update PGA1L_VU 0 = Latch corresponding volume setting into Register Map but do not update volume ...
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... PGA2R_ PGA2L_ MUTE MUTE N Description N/A N/A N PGA_SR[2:0] AUTO_INC Description WM8595 N/A N PGA1R_ PGA1L_ MUTE_ALL MUTE MUTE 1 1 N/A = Not Applicable (no function implemented N/A N N/A N N/A = Not Applicable (no function implemented) PD, Rev 4 ...
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... WM8595 R30 (1Eh) – Input Control Register 1 (INPUT_CTRL1) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read ADCR_SEL[3:0] Write Default 1 0 Function ADCL_SEL[3:0] ADC Input Select ADCR_SEL[3:0] 0000 = IN1L 0001 = IN2L 0010 = IN3L 0011 = IN4L 0100 = IN5L 0101 = IN6L 0110 = Reserved ...
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... N/A = Not Applicable (no function implemented) Description N/A N/A N VOUT2R_TRI VOUT2L_TRI VOUT1R_TRI VOUT1L_TRI N/A N N/A = Not Applicable (no function implemented) Description WM8595 N/A N/A N PGA2L_EN PGA1R_EN PGA1L_EN VOUT2R_EN VOUT2L_EN VOUT1R_EN ...
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... WM8595 R35 (23h) – Bias Control Register (BIAS) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read VMID_SEL[1:0] Write Default 0 0 Function POBCTRL Bias Source for Output Amplifiers 0 = Output amplifiers use master bias 1 = Output amplifiers use fast bias VMIDTOG VMID Power Down Characteristic ...
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... Do not update PGA clock source 1 = Update clock source Figure 48 R36 – PGA Control Register N/A N/A N N/A N N/A = Not Applicable (no function implemented) Description WM8595 PGA_UPD N/A N PGA_SEL[2:0] N PD, Rev 4.1, April 2010 67 ...
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... MCLK1 Pin Function Select 000 = Input to WM8595 001 = Output MCLK2 010 to 111 = Reserved WORDCLK1_SEL[2:0] BCLK1 and LRCLK1 Pins Function Select 000 = Inputs to WM8595 001 = Output BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) PORT1_UPD Port 1 Update ...
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... N/A Default 1 0 Function MCLK2_SEL[2:0] MCLK2 Pin Function Select 000 = Output MCLK1 001 = Input to WM8595 010 = Output MCLK3 011 = Output MCLK4 100 = Output MCLK5 101 to 111 = Reserved BCLK2 and LRCLK2 Pins Function Select WORDCLK2_SEL[2:0] 000 = Output BCLK1 and LRCLK1 001 = Inputs to WM8595 ...
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... WM8595 R42 (2Ah) – Audio Interface MUX Configuration Register 3 (AIF_MUX3) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read DAC1DIN_ DAC1WORDCLK_SEL[2:0] Write SEL[0] Default 0 0 Function DAC1MCLK_SEL[2:0] DAC1MCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved DAC1WORDCLK_ DAC1BCLK and DAC1LRCLK Select ...
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... Latch corresponding DAC2 clock settings into Register Map and update all simultaneously Figure 52 R43 – Audio Interface MUX Configuration Register N/A N/A N DAC2MCLK_SEL[2: N/A = Not Applicable (no function implemented) Description WM8595 DAC2_UPD DAC2DIN_SEL[2: N PD, Rev 4.1, April 2010 71 ...
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... WM8595 R44 (2Ch) – Audio Interface MUX Configuration Register 5 (AIF_MUX5) Bit # 15 14 Read 0 0 Write N/A N/A Default 0 0 Bit # 7 6 Read 0 ADCWORDCLK_SEL[2:0] Write N/A Default 0 0 Function ADCMCLK_SEL[2:0] ADCMCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved ADCWORDCLK_ ADCBCLK and ADCLRCLK Select ...
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... GPIO1_SEL[2:0] GPIO1 Pin Function Select 000 = Source DACDAT1 001 = Source DACDAT2 010 = Source ADCDAT 011 to 100 = Reserved 101 = Input to WM8595 110 = Source GPIO2 111 = Source ADC Data Output GPIO1 Update GPIO1_UPD 0 = Latch corresponding GPIO1 settings into Register Map but do not update 1 = Latch corresponding GPIO1 settings into Register Map and update Figure 54 R45 – ...
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... WM8595 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter ± 0.05dB Passband Passband Ripple Stopband Stopband Attenuation Group Delay DAC Filter – 32kHz to 96kHz ± 0.1dB Passband Passband Ripple Stopband Stopband attenuation f > 0.546fs Group Delay DAC Filter – 176.4kHz to 192kHz ± ...
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... Frequency (Fs) Figure 58 DAC Digital Filter Frequency Response – 192KHz w 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0 2.5 3 Figure 57 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 -0.2 -0.4 -0.6 -0 0.6 0.7 0.8 0.9 1 Figure 59 DAC Digital Filter Ripple – 192kHz 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) PD, Rev 4.1, April 2010 WM8595 0.45 0.5 0.45 0.5 75 ...
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... WM8595 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 60 De-Emphasis Frequency Response (32kHz) Figure 62 De-Emphasis Frequency Response (44.1kHz - Frequency (kHz) Figure 64 De-Emphasis Frequency Response (48kHz 0.5 0 -0.5 -1 -1 Figure 61 De-Emphasis Error (32kHz) Figure 63 De-Emphasis Error (44 ...
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... Magnitude (dB 0.00 0.25 0.50 -20 -40 -60 -80 -100 -120 -140 Frequency Figure 66 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8595 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H( 0.9995z -10 -12 -14 -16 -18 -20 0 ...
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... Decoupling capacitors shown are very low-ESR, multilayer ceramic capacitors and should be placed as near to the WM8595 as possible. Equally good audio performance may be obtained using 0.1μF ceramic capacitors near to the WM8595, with a 10μF electrolytic capacitor nearby. Note that power up time is a function of the VMID2C resistor string setting and the decoupling capacitor C7 ...
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... Other filter architectures may provide equally good results. RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for the use of the WM8595. DEVICE PERFORMANCE: WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – ...
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... WM8595 PACKAGE DIMENSIONS FL: 48 PIN QFN PLASTIC PACKAGE EXPOSED GND PADDLE Symbols Dimensions (mm) MIN NOM A 0.75 0 0.035 0. 0.203 REF A3 b 0.20 0.25 D 7.00 BSC D2 5.55 5.65 E 7.00 BSC E2 5.55 5.65 e 0.5 BSC L 0.35 0.4 Tolerances of Form and Position aaa 0.10 0.08 bbb ccc 0.10 REF JEDEC, MO-220 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. ...
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... Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w WM8595 PD, Rev 4.1, April 2010 81 ...