wm9714l Wolfson Microelectronics plc, wm9714l Datasheet
wm9714l
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wm9714l Summary of contents
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... PLL. The PLL supports a wide range of input clock from 2.048MHz to 78.6MHz. The WM9714L operates at supply voltages from 1.8V to 3.6V. Each section of the chip can be powered down under software control to save power. The device is available in a small leadless 7x7mm QFN package, ideal for use in hand-held portable systems ...
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... WM9714L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 AUDIO OUTPUTS.......................................................................................................... 7 AUDIO INPUTS.............................................................................................................. 8 AUXILIARY MONO DAC (AUXDAC).............................................................................. 8 PCM VOICE DAC (VXDAC) ........................................................................................... 8 AUXILIARY ADC............................................................................................................ 9 COMPARATORS ........................................................................................................... 9 REFERENCE VOLTAGES ............................................................................................. 9 DIGITAL INTERFACE CHARACTERISTICS................................................................ 10 POWER CONSUMPTION ...
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... DC COUPLED (CAPLESS) HEADPHONE OUTPUT ................................................. 112 BTL LOUDSPEAKER OUTPUT ................................................................................. 112 COMBINED HEADSET / BTL EAR SPEAKER........................................................... 112 COMBINED HEADSET / SINGLE-ENDED EAR SPEAKER....................................... 113 JACK INSERT DETECTION ...................................................................................... 113 HOOKSWITCH DETECTION..................................................................................... 114 TYPICAL OUTPUT CONFIGURATIONS ................................................................... 115 PACKAGE DIMENSIONS ..................................................................................118 IMPORTANT NOTICE ........................................................................................119 ADDRESS:................................................................................................................. 119 w WM9714L PP, Rev 3.2, October 2008 3 ...
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... WM9714L PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM9714LGEFL/V -25 to +85 o WM9714LGEFL/RV -25 to +85 Note: Reel quantity = 2,200 w MOISTURE SENSITIVITY PACKAGE 48-lead QFN C (Pb-free) 48-lead QFN C (Pb-free, tape and reel) Pre-Production PEAK SOLDERING LEVEL TEMPERATURE o MSL3 260 C o MSL3 260 C PP, Rev 3.2, October 2008 ...
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... Master Clock B Input / GPIO6 / (ADA output / MASK input) Supply Digital Ground (return path for both DCVDD and DBVDD) Digital Input Serial Data Output from Controller / Input to WM9714L Digital Output Serial Interface Clock Output to Controller Supply Digital Ground (return path for both DCVDD and DBVDD) ...
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... WM9714L PIN NAME 44 GPIO1 / PCMCLK 45 GPIO2 / IRQ 46 GPIO3 / PCMFS 47 GPIO4 / ADA / MASK / PCMDAC 48 GPIO5 / S/PDIF / PCMADC 49 GND_PADDLE Notes recommended that the GND_PADDLE is connected to analogue ground. Refer to the "Recommended External Components" diagram and "Package Dimensions" section for further information. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only ...
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... C, 1kHz signal 48kHz, 24-bit audio data unless MIN TYP MAX -85 -74 50 400 500 -66 0.05 90 400 500 -66 0.05 90 -80 -80 -78 -79 90 =16Ω, THD is L PP, Rev 3.2, October 2008 WM9714L UNIT V rms (rms) mW (rms (rms) mW (rms ...
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... WM9714L AUDIO INPUTS Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, T PARAMETER LINEL/R, MIC1/2A/2B, MONOIN and PCBEEP pins Full Scale Input Signal Level (0dBFS) Input Resistance Input Capacitance Line input to ADC (LINEL, LINER, MONOIN) Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection ...
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... SYMBOL TEST CONDITIONS pin not selected as AUX ADC input MCLK = 24.576MHz o = +25 C, 1kHz signal 48kHz, 24-bit audio data unless otherwise stated. A SYMBOL TEST CONDITIONS V MICBIAS I MICBIAS 20kHz WM9714L MIN TYP MAX AGND AVDD <10 12 ±0.25 ±1 ±2 ±4 ± ...
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... Supply voltages: Reducing the supply voltages also reduces digital supply currents, end therefore results in significant power savings especially in the digital sections of the WM9714L. • Operating mode: Significant power savings can be achieved by always disabling parts of the WM9714L that are not used (e.g. audio ADC, DAC, AUXADC). • ...
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... Note: 1. Worst case duty cycle restricted to 45/ CLK_HIGH t CLK_PERIOD t SYNC_HIGH SYNC t PARAMETER SYMBOL t CLK_PERIOD t CLK_HIGH t CLK_LOW t SYNC_PERIOD t SYNC_HIGH t SYNC_LOW t CLK_LOW t SYNC_LOW SYNC_PERIOD MIN TYP 12.288 81.4 36 40.7 36 40.7 48 20.8 1.3 19.5 PP, Rev 3.2, October 2008 WM9714L MAX UNIT MHz ns 750 kHz µs µs µs 11 ...
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... WM9714L DATA SETUP AND HOLD Figure 2 Data Setup and Hold (50pF External Load) Note: Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9713L. Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise stated ...
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... DON'T DATA PR4 TO 0X20 CARE t S2_PDOWN PARAMETER SYMBOL t S2_PDOWN MIN TYP 2 CLK tfall 2 CLK SYNC SYNC trise 2 DIN tfall 2 DIN DOUT DOUT MIN TYP PP, Rev 3.2, October 2008 WM9714L MAX UNIT MAX UNIT 1.0 µs 13 ...
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... WM9714L COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS) Figure 5 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details. ...
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... PCMADC propagation delay from PCMCLK falling edge Note: 1. PCMCLK period should always be greater than or equal to Voice CLK period. w SYMBOL MIN TYP t 50 PCMY t 20 PCMH t 20 PCML t 10 FSSU t 10 FSH PP, Rev 3.2, October 2008 WM9714L MAX UNIT ...
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... WM9714L PCM AUDIO INTERFACE TIMING – MASTER MODE Figure 8 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V -25°C to +85°C, unless otherwise stated. PARAMETER Audio Data Input Timing Information PCMFS propagation delay from PCMCLK falling edge ...
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... DAC on the WM9714L, which is interfaced via a standard PCM type data interface, which is constructed through optional use the GPIO pins on WM9714L. The audio output data from one or both of the audio ADCs can also be output over this PCM interface, allowing a full voice codec function to be implemented. This PCM interface supports sample rates from 8 to 48ks/s using the standard AC’ ...
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... WM9714L AUDIO PATHS OVERVIEW (Loopback) AC'97 Link ADC Left 00000 = +12dB 11111 = -34.5dB LINEL 00000 = +12dB 11111 = -34.5dB MONOIN PCBEEP 00000 = +12dB 11111 = -34.5dB (Loopback) AC'97 Link ADC Right 00000 = +12dB 11111 = -34.5dB LINER Vmid MIC1 22h: 22h:11-10 13- +12dB Vmid 11 = +30dB MIC2A Vmid ...
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... Pre-Production CLOCK GENERATION WM9714L supports clocking from 2 separate sources, which can be selected via the AC’97 interface: • External clock input MCLKA • External clock input MCLKB The source clock is divided to appropriate frequencies in order to run the AC’97 interface, PCM interface, voice DAC and Hi-fi DSP by means of a programmable divider block. Clock rates may be changed during operation via the AC’ ...
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... WM9714L Figure 10 Clocking Architecture for WM9714L INTERNAL CLOCK FREQUENCIES The internal clock frequencies are defined as follows (refer to Figure 10): • • • 8ks/s voice and HIFI 8ks/s voice only (power save) 16ks/s voice and HIFI 16ks/s voice only (power save) 32ks/s voice and HIFI ...
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... PENDIV 000 (div 16) 2 CLKBX2 0 (Off) 1 CLKAX2 0 (Off) 0 CLKMUX 0 (MCLKA) WM9714L DESCRIPTION Defines clock division ratio for Hi-fi: DSP, ADCs and DACs 000: f 001: f/2 ... 111: f/8 Defines clock division ratio for PCM interface and voice DAC in external clock mode only: 0000: f 0001: f/2 … ...
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... WM9714L PLL MODE The PLL operation is controlled by register 46h (see Table 4) and has two modes of operation: • • The PLL has been optimized for nominal input clock (PLL_IN) frequencies in the range 8.192MHz – 19.661MHz (LF=0) and 2.048MHz – 4.9152MHz (LF=1). Through use of a clock divider (div the input to the PLL frequencies ...
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... OUTPUT (PLL_OUT) 98.304MHz 98.304MHz 98.304MHz 98.304MHz 98.304MHz / F , and is set by N[3:0] and must be in PLL_out PLL_IN 22 and is set by K[21:0] (register 46h, see DIVISION FRACTIONAL REQUIRED DIVISION (K) ( 7.5618 0.5618 7.2818 0.2818 PP, Rev 3.2, October 2008 WM9714L INTEGER DIVISION (N) 12x4* 6x4 ...
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... WM9714L PLL REGISTER PAGE ADDRESS MAPPING The clock division control bits S register 46h using a sub-page address system. The 3 bit pager address allows 8 blocks of 4 bit data words to be accessed whilst the register address is set to 46h. This means that when register address 46h is selected a further 7 cycles of programming are required to set all of the page data bits ...
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... Pre-Production DIGITAL INTERFACES The WM9714L has two interfaces, a data and control AC’97 interface and a data only PCM interface. The AC’97 interface is available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK and RESETB) and is the sole control interface with access to all data streams on the device except for the Voice DAC ...
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... PCM codec function is not enabled then the GPIO pins may be used for other functions. INTERFACE PROTOCOL The WM9714L PCM audio interface is used for the input of data to the Voice DAC and the output of data from the Stereo ADC. When enabled, the PCM audio interface uses four GPIO pins: • ...
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... PCMADC/ PCMDAC Figure 13 PCM Interface Mono Mode (mode A, FSP=0) PCMFS PCMCLK PCMADC/ PCMDAC Figure 14 PCM Interface Mono Mode (mode B, FSP= PCMCLK n-2 n-1 MSB Input Word Length (WL) 1 PCMCLK n-2 n-1 MSB LSB Input Word Length (WL) WM9714L 1/fs n LSB 1/fs n PP, Rev 3.2, October 2008 27 ...
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... WM9714L In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of PCMCLK (selectable by FSP) following a rising edge of PCMFS. Right channel data immediately follows left channel data. Depending on word length, PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of the right channel data and the next sample ...
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... LEFT CHANNEL n-2 n-1 n MSB LSB LEFT CHANNEL n-2 n-1 MSB LEFT CHANNEL 1 BCLK n-2 n-1 LSB MSB 2 S Justified Audio Interface (assuming n-bit word length) WM9714L 1/fs RIGHT CHANNEL n-2 n-1 MSB LSB 1/fs RIGHT CHANNEL n-2 n-1 LSB MSB 1/fs RIGHT CHANNEL 1 BCLK ...
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... WM9714L CONTROL The register bits controlling PCM audio format, word length and operating modes are summarised below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must be set to specify master/slave modes. REGISTER ADDRESS 36h PCM Control Table 8 PCM Codec Control Note: Right justified does not support 32-bit data ...
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... ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing a ‘1’ to the HPF bit (register 5Ch, bit 3). This high pass filter corner frequency can be selected to have different values in WM9714L, to suit applications such as voice where a higher cutoff frequency is required. ...
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... WM9714L RECORD SELECTOR The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the RX signal and the other for the TX signal, so that both sides of the conversation are digitized ...
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... Standard 5:0 RECVOLR 000000 Right ADC Recording Volume Control Standard (GRR=0) XX0000: 0dB XX0001: +1.5dB … (1.5dB steps) XX1111: +22.5dB WM9714L DESCRIPTION Extended (GRL=1) 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB Extended (GRR=1) 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB PP, Rev 3 ...
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... WM9714L REGISTER ADDRESS 14h Record Routing Table 13 Record PGA Routing Control w BIT LABEL DEFAULT 15:14 R2H 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left ADC only 10 = right ADC only 11=mute left and right 13:11 R2HVOL 010 (0dB) Record Mux to Headphone Mixer Path ...
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... Pre-Production AUTOMATIC LEVEL CONTROL The WM9714L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary ...
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... WM9714L When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register ...
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... When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM9714L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record PGA) against a noise gate threshold, NGTH ...
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... DAC. (Contrary to the AC’97 specification, they have no effect on analogue input signals or signals played through the auxiliary DAC. Nevertheless, the ID2 and ID5 bits in the reset register, 00h, are set to ‘1’ to indicate that the WM9714L supports tone control and bass boost.) The DAC output has a PGA for volume control. The DAC sample rate can be controlled by writing to a control register (see “ ...
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... Pre-Production TONE CONTROL / BASS BOOST The WM9714L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: • • ...
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... WM9714L 3D STEREO ENHANCEMENT The 3D stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (L-R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D depth setting controls the degree of stereo expansion introduced by the function. Additionally, the upper and lower limits of the frequency range used for 3D enhancement can be selected using the 3DFILT control bits ...
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... VXDAC to Speaker Mixer Volume (0dB) Control 000 = +6dB … (+3dB steps) 111 = -15dB 7 V2M 1 VXDAC to Mono Mixer Mute Control 1 = Mute mute 6:4 V2MVOL 010 VXDAC to Mono Mixer Volume Control (0dB) 000 = +6dB … (+3dB steps) 111 = -15dB WM9714L DESCRIPTION PP, Rev 3.2, October 2008 41 ...
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... WM9714L REGISTER ADDRESS 3Ch Powerdown (1) 64h AUXDAC Input Control 1Ah AUXDAC Output Control Table 20 AUXDAC Control w BIT LABEL DEFAULT 11 AUXDAC 0 AUXDAC Disable Control 1 = Disabled 0 = Enabled 15 XSLE 0 AUXDAC Input Select Control 0 = From AUXDACVAL[11:0] (for DC signals From AC-Link (for AC signals) 14:12 AUXDAC 000 AUXDAC Input Control (XSLE=1) ...
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... Pre-Production VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION By using an AC’97 Rev2.2 compliant audio interface, the WM9714L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other – any combination is possible). ...
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... WM9714L AUDIO INPUTS The following sections give an overview of the analogue audio input pins and their function. For more information on recommended external components, please refer to the “Applications Information” section. LINE INPUT The LINEL and LINER inputs are designed to record line level signals, and/or to mix into one of the analogue outputs ...
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... DEFAULT 15:14 MICCMPSEL 00 13:12 MPASEL 00 11:10 MPABST 00 9:8 MPBBST 00 WM9714L MICA MICB DESCRIPTION MIC2A/MIC2B Pin Function Control 00 = MIC2A and MIC2B are mic inputs 01 = MIC2A mic input only 10 = MIC2B mic input only 11 = MIC2A and MIC2B are not mic inputs MPA Pre-Amp Source Control 00 = MIC1 01 = MIC2A 10 = MIC2B ...
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... WM9714L SINGLE MIC OPERATION Up to three microphones can be connected in a single-ended configuration. Any one of the three MICs can be selected as the input to MPA using MPASEL[1:0] (Register 22h, bits 13:12). Only the microphone on MIC2B can be selected to MPB. Note that MPABST always sets the gain for the selected MPA input microphone ...
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... Enable MICBIAS output on GPIO8 (pin 12 Disable MICBIAS output on GPIO8 (pin 12) 6 MBOP1EN 1 (On) MICBIAS Output 1 Enable Control 1 = Enable MICBIAS output on MICBIAS (pin 28 Disable MICBIAS output on MICBIAS (pin 28) 5 MBVOL 0 MICBIAS Output Voltage Control 1 = 0.75 x AVDD 0 = 0.9 x AVDD WM9714L DESCRIPTION PP, Rev 3.2, October 2008 47 ...
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... There are two separate interrupt bits, MICDET to e.g. distinguish between one or two microphones connected to the WM9714L, and MICSHT to detect a shorted microphone (mic button press). The microphone current detect threshold is set by MCDTHR[2:0], for MICDET, and MCDSCTHR[1:0] for MICSHT. ...
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... MB2M 1 5 MIC2MBST 0 4:3 MIC2H 11 2:0 MIC2HVOL 010 (0dB) WM9714L DESCRIPTION DESCRIPTION MICA to Mono Mixer Mute Control 1 = Mute mute MICB to Mono Mixer Mute Control 1 = Mute mute MIC to Mono Mixer Boost Control 1 = +20dB 0 = 0dB MIC to Headphone Mixer Path Control 00 = stereo 01 = MICA only ...
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... WM9714L MONOIN INPUT Pin 20 (MONOIN mono input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a phone call, one ADC channel should record the MONOIN signal while the other channel records the MIC signal). The record PGA adjusts the recording volume, and is controlled by register 12h or by the ALC function (see “ ...
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... PCBEEP to Speaker Mixer Volume Control (0dB) 000 = +6dB … (+3dB steps) 111 = -15dB 7 B2M 1 PCBEEP to Mono Mixer Mute Control 1 = Mute mute 6:4 B2MVOL 010 PCBEEP to Mono Mixer Volume Control (0dB) 000 = +6dB … (+3dB steps) 111 = -15dB WM9714L DESCRIPTION PP, Rev 3.2, October 2008 51 ...
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... AUDIO MIXERS MIXER OVERVIEW The WM9714L has four separate low-power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. These mixers are used to drive the audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 and OUT4. There are also two inverters used to provide differential output signals (e ...
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... AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) BIT LABEL DEFAULT 15:13 INV1 000 (OFF) 12:10 INV2 000 (OFF) WM9714L DESCRIPTION INV1 Source Select 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX 011 = HPMIXL 100 = HPMIXR 101 = HPMIXMONO 110 = Reserved 111 = VMID ...
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... WM9714L ANALOGUE AUDIO OUTPUTS The following sections give an overview of the analogue audio output pins. The WM9714L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO - and four outputs capable of driving loads down to 8Ω (loudspeaker / line drivers) – SPKL, SPKR, OUT3 and OUT4 ...
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... HPRVOL 000000 (0dB) BIT LABEL DEFAULT 15:14 MONO 00 (Vmid) WM9714L DESCRIPTION HPL Mute Control 1 = Mute mute HPL Zero Cross Control 1 = Zero cross enabled (change volume only on zero crossings, or after time-out Zero cross disabled (change volume immediately) HPL Volume Control 000000 = 0dB (maximum) … ...
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... WM9714L REGISTER ADDRESS 08h MONO Vol Table 35 Mono PGA Control SPEAKER OUTPUTS – SPKL AND SPKR The SPKL and SPKR (pins 35 and 36) are designed to drive a loudspeaker load down to 8Ω and can also be used as line outputs and headphone outputs. They are designed to drive an 8Ω load AC coupled BTL (capless) configuration ...
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... BIT LABEL DEFAULT 3:2 OUT3 00 (Vmid) 1:0 OUT4 00 (Vmid) WM9714L DESCRIPTION SPKL Mute Control 1 = Mute mute SPKL Zero Cross Control 1 = Zero cross enabled (change volume only on zero crossings, or after time-out Zero cross disabled (change volume immediately) SPKL Volume Control 000000 = 0dB (maximum) … ...
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... If the chip temperature reaches approximately 150°C, and the TI bit is set, the WM9714L deasserts GPIO bit 11 in register 54h, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt Control” section). ...
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... GPIO is pulled low by a switch on the socket. When the jack is removed the GPIO is pulled high by a resistor. If the JIEN bit is set, the WM9714L automatically switches between headphone and any other output configuration, typically ear speaker or stereo speaker that has been set up in the Powerdown and Output PGA Mux Select registers ...
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... WM9714L speaker driver are disabled and internally connected to VREF on jack insert. This maintains VREF at those outputs and helps prevent pops when the outputs are enabled. Finally if the user wishes to DC couple the headphone outputs the user needs to select between OUT3 and OUT4 as the mid-rail output buffer driver. The selected mid-rail output buffer is enabled on jack insert ...
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... OUT4 Ear Speaker Selected. OUT3 DC Coupled Headphone Selected Jack Insert Detection Enabled. Headphone plugged out. No Ear Speaker Selected Jack Insert Detection Enabled. Headphone plugged out. OUT4 Ear Speaker Selected. Table 44 Jack Insertion / Auto-Switching (2) w WM9714L PP, Rev 3.2, October 2008 61 ...
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... WM9714L DIGITAL AUDIO (S/PDIF) OUTPUT The WM9714L supports the S/PDIF standard. Pins 48 & 12 can be used to output the S/PDIF data. Note that pins 48 & 12 can also be used as GPIO pins. The GE5 & GE8 bits (register 56h, bit 5 & bit 8) select between GPIO and S/PDIF functionality for pins 48 & 12 respectively (see “GPIO and Interrupt control” ...
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... S/PDIF Non-audio Indication Control 0 = PCM data 1 = Non-PCM data (e. DTS) 0 PRO 0 S/PDIF Professional Indication Control 0 = Consumer mode 1 = Professional mode 4 ADCO 0 S/PDIF Data Source Control 0 = From SDATAOUT (pin Output from audio ADC Note: Slot selected by SPSA in 2Ah WM9714L DESCRIPTION PP, Rev 3.2, October 2008 63 ...
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... WM9714L AUXILIARY ADC The WM9714L includes a very low power, 12-bit successive approximation type ADC which can be used for battery and auxiliary measurements. Three pins that can be used as auxiliary ADC inputs: • • • Pins 29 and 30 are also used as comparator inputs (see “Battery Alarm and Analogue Comparators” ...
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... Pre-Production INITIATION OF MEASUREMENTS The WM9714L AUXADC interface supports both polling routines and DMA (direct memory access) to control the flow of data from the AUX ADC to the host CPU polling routine, the CPU starts each measurement individually by writing to the POLL bit (register 74h, bit 9) ...
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... Note: Only one bit in 74h[7:4] should be set at any one time Table 48 AUX ADC Control (Measurement Types) The WM9714L performs a single measurement – either in polling mode or continuously, as indicated by the CTC bit. The type of measurement is specified by the ADCSEL[7:4] bits. Only one of the ADCSEL[7:4] bits should be set. ...
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... Table 49 AUX ADC Data To avoid losing data that has not yet been read, the WM9714L can delay overwriting register 7Ah with new conversions until the old data has been read. This function is enabled using the WAIT bit. If the SLEN bit is set to ‘1’, then the ADC data appears on the AC-Link slot selected by the SLT control bits, as shown below. The Slot 0 ‘ ...
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... WM9714L REGISTER ADDRESS 76h Table 50 Returning AUX ADC Data Through an AC-Link Time Slot MASK INPUT CONTROL Sources of glitch noise, such as the signals driving an LCD display, may feed through to the AUX ADC inputs and affect measurement accuracy. In order to minimise this effect, a signal may be applied to MASK (pin 47 / pin 3) to delay or synchronise the sampling of any input to the ADC ...
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... AUXADC input to be either COMP1 (ADCSEL = 100) or COMP2 (ADCSEL = 101) (see also Auxiliary ADC Inputs). w < VREF × (R1+R2+R3) / (R2+R3) BATT < VREF × (R1+R2+R3 BATT gets close to the low battery threshold, spurious BATT [Hz (2π C × (R1 || (R2+R3))) WM9714L = V / ALARM BATT , n . This is achieved simply BATT PP, Rev 3.2, October 2008 69 ...
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... The comparator output signals are passed to the GPIO logic block (see “GPIO and Interrupt Control” section), where they can be used to send an interrupt to the CPU via the AC-Link or via the IRQ pin, and / or to wake up the WM9714L from sleep mode. COMP1/AUX1 (pin 29) corresponds to GPIO bit 15 and COMP2/AUX2 (pin30) to bit 14. ...
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... COMP2DEL is non-zero), then GPIO bit 14 does not change state immediately, and no interrupt is generated. Instead, the WM9714L starts a delay timer and checks COMP2 again after the delay time has passed. If COMP2 is still active, then the GPIO bit is set and an interrupt may be generated (depending on the state of the GW14 bit) ...
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... Independently of the GPIO pins, the WM9714L also has seven virtual GPIOs. These are signals from inside the WM9714L, which are treated as if they were GPIO input signals. From a software perspective, virtual GPIOs are the same as GPIO pins, but they cannot be set up as outputs, and are not tied to an actual pin ...
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... Internal ADA (ADC Data Available) Signal enabled only when AUXADC is active [ADA] Internal COMP2 output (Low Battery Alarm) - enabled only when COMP2 is on [COMP2] - Internal COMP1 output (Dead Battery Alarm) [COMP1] enabled only when COMP1 is on WM9714L DESCRIPTION PP, Rev 3.2, October 2008 73 ...
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... If the system CPU cannot execute such an interrupt routine, it may be preferable to switch internal signals directly onto the GPIO pins. However, in this case the interrupt signals cannot be made sticky, and more GPIO pins are tied up both on the WM9714L and on the CPU. w BIT ...
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... GE8 1 GPIO8 (Pin 12) Function Control 0 = Pin 12 is not controlled by GPIO logic 1 = Pin 12 is controlled by GPIO logic Note: When GE8=0, WM9714L DESCRIPTION set GC2=0 in 4Ch to output IRQ set GC4=0 in 4Ch to output ADA set GC4=1 in 4Ch to input MASK set GC5=0 in 4Ch to output S/PDIF ...
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... POWER MANAGEMENT INTRODUCTION The WM9714L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register Powerdown registers 3Ch and 3Eh. Each particular circuit block is active when both the relevant bit in register 26h AND the relevant bit in the Powerdown registers 3Ch and 3Eh are set to ‘ ...
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... Disabled 0 = Enabled 3 HPLX 1 Left Headphone Mixer Disable Control (disabled Disabled 0 = Enabled 2 HPRX 1 Right Headphone Mixer Disable Control (disabled Disabled 0 = Enabled 1 SPKX 1 Speaker Mixer Disable Control (disabled Disabled 0 = Enabled Mono Mixer Disable Control (disabled Disabled 0 = Enabled WM9714L DESCRIPTION PP, Rev 3.2, October 2008 77 ...
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... WM9714L REGISTER ADDRESS 3Eh Powerdown (2) Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except when VREF and VMID1M are both OFF). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled. ...
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... Mixer output inverters: see “Mixer output Inverters” section. Inverters are disabled by default. SLEEP MODE Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9714L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits ...
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... Digitiser Reg 78h Digitiser Reg 3 PRP 0 7Ah Digitiser Read Back 0 ADCSRC 7Ch Vendor ID1 7Eh Vendor ID2 Table 63 WM9714L Register Map Note: Register 46h provides access to a sub-page address system to set the SE2 SE1 SE0 ID9 ID8 ...
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... Indicates that the WM9714L does not support simulated stereo 1 Indicates that the WM9714L supports bass and treble control 0 Indicates that the WM9714L does not support modem functions 0 Indicates that the WM9714L does not have a dedicated microphone ADC DEFAULT DESCRIPTION 1 (mute) SPKL Mute Control 1 = Mute mute 0 (disabled) ...
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... WM9714L REGISTER BIT LABEL ADDRESS 04h 15 MUL 14 ZCL 13:8 HPL VOL 7 MUR 6 ZCR 5:0 HPR VOL Register 04h controls the headphone output pins, HPL and HPR. REGISTER BIT LABEL ADDRESS 06h 15 MU4 14 ZC4 13:8 OUT4VOL 7 MU3 6 ZC3 5:0 OUT3VOL Register 06h controls the analogue output pins OUT3 and OUT4. ...
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... LINEL to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB 01000 (0dB) LINER to Mixers Volume Control 00000 = +12dB … (1.5dB steps) 11111 = -34.5dB WM9714L REFER TO Analogue Inputs; Analogue Audio Outputs REFER TO Analogue Inputs, Line Input PP, Rev 3.2, October 2008 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 0Ch 15 D2H 14 D2S 13 D2M 12:8 DACLVOL 4:0 DACRVOL Register 0Ch controls the audio DACs (but not AUXDAC). REGISTER BIT LABEL ADDRESS 0Eh 12:8 MICAVOL 4:0 MICBVOL Register 0Eh controls the microphone PGA volume (MICA and MICB). REGISTER BIT LABEL ADDRESS ...
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... Right ADC PGA Gain Range Control 1 = Extended 0 = Standard 000000 (0dB) Right ADC Recording Volume Control Standard (GRR=0) XX0000: 0dB XX0001: +1.5dB … (1.5dB steps) XX1111: +22.5dB WM9714L REFER TO Audio ADC, Record Gain Extended (GRL=1) 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB Extended (GRR=1) 000000: -17 ...
Page 86
... WM9714L REGISTER BIT LABEL ADDRESS 14h 15:14 R2H 13:11 R2HVOL 10:9 R2M 8 R2MBST 6 RECBST 5:3 RECSL 2:0 RECSR Register 14h controls the.record selector and the ADC to mono mixer path. w DEFAULT DESCRIPTION 11 (mute) Record Mux to Headphone Mixer Path Control 00 = stereo 01 = left record mux only 10 = right rec mux only ...
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... VXDAC to Mono Mixer Mute Control 1 = Mute mute 010 (0dB) VXDAC to Mono Mixer Volume Control 000 = +6dB … (+3dB steps) 111 = -15dB WM9714L REFER TO Analogue Inputs, PCBEEP Input REFER TO Audio Mixers, Side Tone Control PP, Rev 3.2, October 2008 87 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 1Ah 15 A2H 14:12 A2HVOL 11 A2S 10:8 A2SVOL 7 A2M 6:4 A2MVOL Register 1Ah controls the output signal of the auxiliary DAC. w DEFAULT DESCRIPTION 1 (mute) AUXDAC to Headphone Mixer Mute Control 1 = Mute mute 010 (0dB) AUXDAC to Headphone Mixer Volume Control 000 = +6dB … ...
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... HPR Source Control 00 = VMID input (tri-stated if HPR is disabled HPMIXR 11 = Reserved 00 (VMID) OUT3 Source Control 00 = VMID input (tri-stated if OUT3 is disabled INV1 11 = Reserved 00 (VMID) OUT4 Source Control 00 = VMID input (tri-stated if OUT4 is disabled INV2 11 = Reserved WM9714L REFER TO Analogue Audio Outputs PP, Rev 3.2, October 2008 89 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 1Eh 15:13 INV1 12:10 INV2 5 3DLC 4 3DUC 3:0 3DDEPTH Register 1Eh controls 3D stereo enhancement for the audio DACs and input muxes to the output inverters INV1 and INV2. w DEFAULT DESCRIPTION 000 (Z ) INV1 Source Select H 000 = No input (tri-stated) 001 = MONOMIX 010 = SPKMIX ...
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... Low (4kHz at 48kHz sampling) 1111 (off) Treble Intensity Control 0000 = +9dB 0001 = +9dB … (1.5dB steps) 0111 = 0dB … (1.5dB steps) 1011-1110 = -6dB 1111 = Bypass (off) WM9714L REFER TO Audio DACs, Tone Control / Bass Boost BB=1 0000 = 15dB … (1dB steps) 1110 = 1dB 1111 = Bypass (off) PP, Rev 3 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 22h 15:14 MICCMP SEL 13:12 MPASEL 11:10 MPABST 9:8 MPBBST 7 MBOP2EN 6 MBOP1EN 5 MBVOL 4:2 MCDTHR 1:0 MCDSCTHR Register 22h controls the microphone input configuration and microphone bias and detect configuration. w DEFAULT DESCRIPTION 00 (mics) MIC2A/MIC2B Pin Function Control 00 = MIC2A and MIC2B are microphone inputs ...
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... Analogue Mixers Ready (Read Only Analogue mixers ready 0 = Analogue mixers not ready 0 Stereo DAC Ready (Read Only DAC ready 0 = DAC not ready 0 Stereo ADC Ready (Read Only ADC ready 0 = ADC not ready WM9714L REFER TO Analogue Audio Outputs REFER TO Power Management PP, Rev 3.2, October 2008 93 ...
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... LDAC 7 SDAC 6 CDAC 3 VRM 2 SPDIF 1 DRA 0 VRA Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9714L supports. REGISTER BIT LABEL ADDRESS 2Ah 10 SPCV 5:4 SPSA 2 SEN 0 VRA Register 2Ah controls the S/PDIF output and variable rate audio. ...
Page 95
... Stereo ADC Sample Rate Control 1F40h = 8kHz 2B11h = 11.025kHz 2EE0h = 12kHz 3E80h = 16kHz 5622h = 22.05kHz 5DC0h = 24kHz 7D00h = 32kHz AC44h = 44.1kHz BB80h = 48kHz Any other value defaults to the nearest supported sample rate WM9714L REFER TO Variable Rate Audio / Sample Rate Conversion PP, Rev 3.2, October 2008 95 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 36h 15 CTRL 14:13 MODE 11:9 DIV 8 VDACOSR FSP 5:4 SEL 3:2 WL 1:0 FMT Register 36h controls the PCM codec. w DEFAULT DESCRIPTION 0 (GPIO reg) GPIO Pin Configuration Control 0 = GPIO pins used as GPIOs 1 = GPIO pins used as PCM interface 10 (master PCM Interface Mode Control ...
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... S/PDIF Pre-emphasis Indication Control pre-emphasis 1 = 50/15µs pre-emphasis 0 S/PDIF Copyright Indication Control 0 = Copyright not asserted 1 = Copyright asserted 0 S/PDIF Non-audio Indication Control 0 = PCM data 1 = Non-PCM data 0 S/PDIF Professional Indication Control 0 = Consumer mode 1 = Professional mode WM9714L REFER TO Digital Audio (S/PDIF) Output PP, Rev 3.2, October 2008 97 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 3Ch 15 PD15 14 VMID1M 13 TSHUT 12 VXDAC 11 AUXDAC 10 VREF 9 PLL 7 DACL 6 DACR 5 ADCL 4 ADCR 3 HPLX 2 HPRX 1 SPKX “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0. Register 3Ch is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 3Ch AND register 26h ...
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... MONOIN PGA Disable Control 1 = Disabled 0 = Enabled 1 (disabled) MICA PGA Disable Control 1 = Disabled 0 = Enabled 1 (disabled) MICB PGA Disable Control 1 = Disabled 0 = Enabled 1 (disabled) Mic Pre-amp MPA Disable Control 1 = Disabled 0 = Enabled 1 (disabled) Mic Pre-amp MPB Disable Control 1 = Disabled 0 = Enabled WM9714L REFER TO Power Management PP, Rev 3.2, October 2008 99 ...
Page 100
... WM9714L REGISTER BIT LABEL ADDRESS 40h 13 3DE 7 LB Register 40h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9714L. REGISTER BIT LABEL ADDRESS 42h 6 MONO 5 SPKL 4 SPKR 3 HPL 2 HPR 1 OUT3 0 OUT4 Register 42h controls power-up conditions for output PGAs. ...
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... AUXADC Clock Division Control 000 = f/16 001 = f/12 010 = f/8 011 = f/6 100 = f/4 101 = f/3 110 = f/2 111 = f 0 (Off) MCLKB Multiplier Control 0 = Normal 1 = Multiply (Off) MCLKA Multiplier Control 0 = Normal 1 = Multiply (MCLKA) External Clock Source Control 0 = Use MCLKA 1 = Use MCLKB WM9714L REFER TO Clock Generation PP, Rev 3.2, October 2008 101 ...
Page 102
... WM9714L REGISTER BIT LABEL ADDRESS 15:12 N[3:0] 46h SDM 9 DIVSEL 8 DIVCTL 6:4 PGADDR 3:0 PGDATA Register 46h controls PLL clock generation. w DEFAULT DESCRIPTION 0000 (div by 1) PLL N Divide Control 0000 = Divide by 1 0001 = Divide by 1 0010 = Divide by 2 … 1111 = Divide (normal) PLL Low Frequency Input Control 1 = Low frequency mode (input clock < ...
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... GPIO4 (Pin 47) Function Control 0 = Pin 47 is not controlled by GPIO logic 1 = Pin 47 is controlled by GPIO logic 1 (GPIO) GPIO2 (Pin 45) Function Control 0 = Pin 45 is not controlled by GPIO logic 1 = Pin 45 is controlled by GPIO logic WM9714L REFER TO GPIO and Interrupt Control Output (GCn = CMOS output ...
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... WM9714L REGISTER BIT LABEL ADDRESS 58h 15:8 PU 7:0 PD Register 56h controls GPIO pull-up/down. REGISTER BIT LABEL ADDRESS 5Ah 15:13 COMP2DEL 8 RSTDIS 7:6 JSEL 5:4 HPMODE 3:2 DIE REV 1 WAKEEN 0 IRQ INV Register 5Ah controls several additional functions. w DEFAULT DESCRIPTION 01000000 GPIO Pin Pull-Up Control 1 = Enables weak pull-up on GPIO pins ...
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... HPF enabled 1 = HPF disabled 00 (slots 3, 4) ADC Data Slot Mapping Control Left Data 00 = Slot Slot Slot Slot 10 WM9714L REFER TO Audio DACs, Stereo DACs Battery Alarm Power Management Digital Audio (S/PDIF) Output Audio ADC Audio ADC, ADC Slot Right Data ...
Page 106
... WM9714L REGISTER BIT LABEL ADDRESS 60h 15:12 ALCL 11:8 HLD 7:4 DCY 3:0 ATK 62h 15:14 ALCSEL 13:11 MAXGAIN 10:9 ZC TIMEOUT 7 NGAT 5 NGG 4:0 NGTH Registers 60h and 62h control the ALC and Noise Gate functions. w DEFAULT DESCRIPTION 1011 (-12dB) ALC Target Level Control 0000 = -28.5dBFS … (1.5dB steps) ...
Page 107
... Enable AUX3 measurement (SPKVDD/3) 0 AUX2 Measurement Enable Control 0 = Disable AUX2 measurement (pin 30 Enable AUX2 measurement (pin 30) 0 AUX1 Measurement Enable Control 0 = Disable AUX1 measurement (pin 29 Enable AUX1 measurement (pin 29) WM9714L REFER TO Auxiliary DAC REFER TO AUXADC PP, Rev 3.2, October 2008 107 ...
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... WM9714L REGISTER BIT LABEL ADDRESS 76h 9:8 CR 7:4 DEL 3 SLEN 2:0 SLT Registers 76h controls the AUXADC measurement timing. REGISTER BIT LABEL ADDRESS 78h 15:14 PRP 9 WAIT 7:6 MSK Register 78h control the physical properties of the AUXADC. w DEFAULT DESCRIPTION 00 (93.75Hz) Continuous Mode Conversion Rate DEL < 1111 ...
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... ADDRESS 7Ch 15:8 F7:0 7:0 S7:0 7Eh 15:8 T7:0 7:0 REV7:0 Register 7Ch and 7Eh are read-only registers that indicate to the driver that the codec is a WM9714L. w DEFAULT DESCRIPTION 000 (none) AUXADC Source 000 = No measurement 001 = Reserved 010 = Reserved 011 = Reserved 100 = COMP1/AUX1 measurement (pin 29) 101 = COMP2/AUX2 measurement (pin 30) ...
Page 110
... WM9714L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Component Diagram w Pre-Production PP, Rev 3.2, October 2008 110 ...
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... The function of R1 and protect the line outputs from damage when used improperly. AC-COUPLED HEADPHONE OUTPUT The circuit diagram below shows how to connect a stereo headphone to the WM9714L. Figure 30 Simple Headphone Output Circuit Diagram The DC blocking capacitors C1 and C2 together with the load resistance determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. For example, with a 16Ω ...
Page 112
... If the DC coupled output is connected to the line- grounded piece of equipment, then OUT3 becomes short-circuited. Although the built-in short circuit protection will prevent any damage to the WM9714L, the audio signal will not be transmitted properly. OUT3 cannot be used for another purpose BTL LOUDSPEAKER OUTPUT SPKL and SPKR can differentially drive a mono 8Ω ...
Page 113
... The circuit requires a headphone socket with a switch that closes on insertion (for using sockets with a switch that opens on insertion, please refer to Application Note WAN0182). It detects both headphones and phone headsets. Any GPIO pin can be used, provided that it is configured as an input. w WM9714L PP, Rev 3.2, October 2008 113 ...
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... WM9714L HOOKSWITCH DETECTION Alternatively a headphone socket with a switch that opens on insertion can be used. For this mode of operation the GPIO input must be inverted. The circuit diagram below shows how to detect when the “hookswitch” phone headset is pressed (pressing the hookswitch is equivalent to lifting the receiver in a stationary telephone). ...
Page 115
... Pre-Production TYPICAL OUTPUT CONFIGURATIONS The WM9714L has three outputs capable of driving loads down to 16Ω (headphone / line drivers) – HPL, HPR and MONO - and four outputs capable of driving loads down to 8Ω (loudspeaker / line drivers) – SPKL, SPKR, OUT3 and OUT4. The combination of output drivers, mixers and mixer inverters means that many output configurations can be supported ...
Page 116
... WM9714L MONO SPEAKER Figure 38 shows a typical output configuration for mono speaker with headphones, ear speaker and hands-free operation. The table shows suggested mixer outputs to select for each output PGA for a given operating scenario. (Note the inverted mixer outputs can be achieved using the mixer output inverters INV1 and INV2) ...
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... PGA for a given operating scenario. (Note the inverted mixer outputs can be achieved using the mixer output inverters INV1 and INV2). When using this configuration note that AVDD, HPVDD and SPKVDD must all be at the same voltage to achieve the best performance. Figure 39 WM9714L Mono Speaker Configuration w WM9714L PP, Rev 3.2, October 2008 ...
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... WM9714L PACKAGE DIMENSIONS FL: 48 PIN QFN PLASTIC PACKAGE EXPOSED GROUND PADDLE BOTTOM VIEW (A3) SIDE VIEW C SEATING PLANE W (A3 Exposed lead Half etch tie bar Symbols Dimensions (mm) MIN NOM 0.80 0. 0.02 A1 0.20 REF A3 0.18 0.25 b 7.00 BSC D 5.00 5.15 D2 7.00 BSC E 5.00 5.15 E2 0.5 BSC e 0.213 G 0 ...
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... Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w WM9714L PP, Rev 3.2, October 2008 119 ...