wm9713 Wolfson Microelectronics plc, wm9713 Datasheet - Page 61

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wm9713

Manufacturer Part Number
wm9713
Description
Ac?97 Audio + Touchpanel Codec
Manufacturer
Wolfson Microelectronics plc
Datasheet

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Pre-Production
w
speaker driver are disabled and internally connected to VREF on jack insert. This maintains VREF at
those outputs and helps prevent pops when the outputs are enabled.
Finally if the user wishes to DC couple the headphone outputs the user needs to select between
OUT3 and OUT4 as the mid-rail output buffer driver. The selected mid-rail output buffer is enabled on
jack insert. On jack out it defaults to whatever configuration has been set up in the Powerdown and
Output PGA Mux Select registers.
Table 42 DC Coupled Headphone Configuration
In summary:
JIEN not set: Outputs work as normal as selected in the Powerdown and Output PGA Mux Select
registers.
JIEN set: On jack insert GPIO1/6/7/8 is pulled low, HPL and HPR are enabled, DCDRVSEL decides
if the headphones are DC or AC coupled and configures OUT3 or OUT4 to suit, EARSPKSEL
decides if MONO, OUT3 or OUT4 need to be tri-stated to ensure no sound out on the ear-speaker
and finally all other outputs are disabled as explained above to prevent pops on re-enabling.
On jack out GPIO1/6/7/8 is pulled high, the outputs work as normal as selected in the Powerdown
and Output PGA Mux Select registers except that HPL Volume is controlled by EARSPKSEL to
ensure correct ear speaker operation.
Table 43 Jack Insertion / Auto-Switching (1)
24h
Output Volume
Mapping (Jack
Insert)
24h Output
Volume
Mapping
(Jack
Insert)
5Ah
Additional
Functions
(1)
REGISTER
ADDRESS
REGISTER
ADDRESS
4
7:6
BIT
3:2
BIT
JIEN
JSEL
LABEL
DCDRVSEL
LABEL
0 (OFF)
00
(GPIO1)
DEFAULT
DEFAULT
00
Jack Insert Control
0 = Disable jack insert circuitry
1 = Enable jack insert circuitry
Jack Detect Pin Input Control
00 = GPIO1
01 = GPIO6
10 = GPIO7
11 = GPIO8
Jack Insert Headphone DC Reference
Control
00 = AC coupled headphones, no DC
source
01 = OUT3 is mid-rail output buffer
10 = Reserved
11 = OUT4 is mid-rail output buffer
DESCRIPTION
DESCRIPTION
PP Rev 3.2 September 2008
WM9713L
61

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