wm9704m Wolfson Microelectronics plc, wm9704m Datasheet
wm9704m
Related parts for wm9704m
wm9704m Summary of contents
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... In modem mode the device supports simultaneous modem and stereo playback. WM9704M is interchangeable with AC'97 Codecs from Wolfson and other suppliers in the basic Revision 2.1 mode. WM9704M is fully operable with 3. mixed 3.3/5.0V supplies and is packaged in an industry standard 48-pin TQFP package. BLOCK DIAGRAM VOL/ ...
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... WM9704M PIN CONFIGURATION DVDD1 1 XTLIN 2 XTLOUT 3 DVSS1 4 SDATAOUT 5 BITCLK 6 DVSS2 7 SDATAIN 8 DVDD2 9 SYNC 10 RESETB 11 PCBEEP ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits ...
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... AVDD -100mV +100mV AVSS Near rail to AVDD +100mV rail -100mV 2/5 AVDD AVDD/2 3/5 AVDD 75 Buffered CAP2 Buffered CAP2 Buffered CAP2 Buffered CAP2 -5 - Rev 3.2 January 2001 WM9704M UNIT UNIT kohms ...
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... WM9704M Test Characteristics: AVDD = 5V, GND = 0V …………..T DVDD = 3.3V, GND = 0V …………..T PARAMETER DAC Circuit Specifications (AVDD = 5V) 48kHz sampling SNR A-weighted (Note 1) Full scale output voltage THD Frequency response Transition band Stop band Out of band rejection Spurious tone reduction ...
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... C to +70 C, unless otherwise stated A SYMBOL TEST CONDITIONS V = 1.65V REF -9dBFS input 20 to 20kHz -3dBV input At any gain At max gain At 0db gain At max gain At 0db gain 20 to 20kHz WM9704M MIN TYP MAX 82 0 19,200 19,200 28,800 28,800 - 0.7 0 ...
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... WM9704M PIN DESCRIPTION PIN NAME 1 DVDD1 2 XTLIN 3 XTLOUT 4 DVSS1 5 SDATAOUT 6 BITCLK 7 DVSS2 8 SDATAIN 9 DVDD2 SYNC 10 11 RESETB PCBEEP 12 13 PHONE AUXL 14 15 AUXR VIDEOL 16 17 VIDEOR CDL 18 19 CDGND CDR 20 21 MIC1 MIC2 22 23 LINEINL LINEINR 24 25 AVDD1 AVSS1 26 27 VREF(1) ...
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... C to +70 A SLOT 1 SLOT 2 SYNC WRITE DON’T DATA PR4 TO 0X20 CARE t S2_PDOWN SYMBOL t S2_PDOWN t RST_LOW SYMBOL t RST_LOW t RST2_CLK WM9704M o C, unless otherwise stated o C, unless otherwise stated MIN TYP MAX 1.0 t RST2CLK MIN TYP MAX 1.0 162.8 PD Rev 3.2 January 2001 UNIT s UNIT s ns ...
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... WM9704M WARM RESET BIT_CLK Figure 3 Warm Reset Timing PARAMETER SYNC active high pulse width SYNC inactive to BIT_CLK startup delay CLOCK SPECIFICATIONS BIT_CLK Figure 4 Clock Specifications (50pF External Load) PARAMETER BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BIT_CLK high pulse width (Note 1) ...
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... DOUT DOUT SYMBOL trise tfall trise tfall trise trise trise tfall MIN TYP MAX 15.0 5.0 HOLD MIN TYP MAX 4 CLK 4 CLK 4 SYNC 4 SYNC 4 DIN 4 DIN 4 DOUT 4 DOUT PD Rev 3.2 January 2001 WM9704M UNIT ns ns UNIT ...
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... WM9704M SYSTEM INFORMATION RESET BITCLK AC’97 SYNC DIGITAL SDATAIN CONTROLLER SDATAOUT { CHIP SELECT Figure 7 WM9704M in a Typical Application WOLFSON MICROELECTRONICS LTD CD, VIDEO, MIC1 AUX, LINEIN MIC2 PCBEEP WM9704M 10 (MODEM MODE CID0 45 CID1 46 MODE0 = 1 43 MODE1 = GPIO [1:3] XTAL ...
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... Therefore, for the DAC, 16-bit words will be downloaded into the Codec from the controller, along with padding make the 16-bit word up to 20-bit length. In this case, the WM9704M will process the 16-bit word along with 0 padding bits in the 2 LSB locations (to make 18-bit). At the ADC output, WM9704M will provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’ ...
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... WM9704M MODEM MODE In Modem mode the modem Tx data is mapped onto the rear DACs. Rear DAC sample rates are set by the Modem Tx sample rate register 40h, and extended modem capability register 3Ch indicates Line1 is supported. The following features are supported in Modem Mode: Vendor ID reads back WML4 Headphone channel flagged as ‘ ...
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... Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to setting the POP bit in register 20h result, the readback value of this bit is fixed as '1', and attempts to change it will be ignored. POP bit is set to one and cannot be re-set. WOLFSON MICROELECTRONICS LTD WM9704M 2 S output pins to support multi-channel operation. PD Rev 3.2 January 2001 ...
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... WM9704M VARIABLE SAMPLE RATE SUPPORT The DACs and ADCs on this device support all the recommended sample rates specified in the Intel Rev 2.1 specification for both audio and modem rates. Default rates are 48ks/s. If alternative rates are selected, the AC’97 interface continues to run at 48k words per second, but data is transferred across the link in bursts such that the net sample rate selected is achieved the AC’ ...
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... Volume Table 4 Gain Control Register Location Versus Mode and ID MASTER/SLAVE ID0/1 SUPPORT WM9704M supports operation as either a master or a slave codec. Configuration of the device as either a master slave, is selected by tying the ID pins CID0 and CID1, pins 45 and 46 on the package. Fundamentally, a device identified as a master (ID = 00) produces BITCLK as an output, whereas a slave (any other ID) must be provided with BITCLK as an input ...
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... New definitions for Slave Codec Register Access Table 8 Slave Codec Register Access Slot 0-Bit Definitions CONTROL INTERFACE A digital interface has been provided to control the WM9704M and transfer data to and from it. This serial interface is compatible with the Intel AC’97 specification as illustrated in the System Diagram (Figure 7). ...
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... Production Data AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL The WM9704M incorporates a 5-pin digital serial interface that links it to the AC’97 controller. AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. ...
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... SYNC is low is defined as the “Data Phase”. Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that the WM9704M be implemented as a static design to allow its register contents to remain intact when entering a power savings mode. ...
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... As an example, consider an 8-bit sample stream that is being played out to one of the WM9704M’s DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit positions, which are stuffed with 0s by the AC’ ...
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... Audio output frame slots are used to send surround sound data to extra DAC channels. These slots are supported by WM9704M in Revision 2.1 and modem modes. Note that the data in the surround sound slots will only be applied to the front DAC. The slots used depend on the Codec ID configuration (see Table 7) ...
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... Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the WM9704M is in the “Codec Ready” state or not. If the “Codec Ready” bit this indicates that the WM9704M is not ready for normal operation. This condition is normal following the desertion of power on reset for example, while the WM9704M’ ...
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... SLOT 2: STATUS DATA PORT The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3:0) If slot 2 is tagged “invalid” by the WM9704M, then the entire slot will be stuffed with 0s by the WM9704M. WOLFSON MICROELECTRONICS LTD WM9704M SAMPLES SYNC ASSERTION HERE SYNC AC’ ...
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... SLOT 12: GPIO functions supported AC-LINK LOW POWER MODE The AC-link signals can be placed in a low power mode. When the WM9704M’s Powerdown Register (26h), is programmed to the appropriate value, both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level. ...
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... BIT_CLK. Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the WM9704M. The WM9704M will not respond with the activation of BIT_CLK until SYNC has been sampled low again by the WM9704M ...
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... Support for the MSB of the volume level is not provided by the WM9704M. If the MSB is written to, then the WM9704M detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9704M interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it ...
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... Below is a summary of each bit and its function. Only the MIX, MS and LPBK bits are supported by the WM9704M. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements ...
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... Production Data 3D CONTROL REGISTER (INDEX 22H) This register is used to control the centre and/or depth of the 3D stereo enhancement function built into of the AC ‘97 component. Only the depth bits DP0 to 3 have effect in the WM9704M. DP3…DP0 RESERVED REGISTER (INDEX 24H) This register was originally specified to control what sample rate AC’97 is sending or receiving samples for the optional modem in and out ...
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... Figure 13 illustrates one example procedure complete powerdown of the WM9704M. From normal operation sequential writes to the Powerdown Register are performed to powerdown the WM9704M a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9704M’s digital interface (AC-link). ...
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... REV 2.1 REGISTERS (INDEX 28H T0 58H) These registers are specified as to use in Rev 2.1 of the AC’97 specification and have the following functions on the WM9704M: REGISTER 28H – EXTENDED AUDIO ID The Extended Audio ID register is a read only register that identifies which extended audio features are supported (in addition to the original AC’ ...
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... Note: for AMC ’97 parts the audio and modem AFE should be logically independent (writes to register 0h resets audio only). LIN1 = 1 indicates 1st line is supported – set when WM9704M is in Modem mode LIN2 = 1 indicates 2nd line is supported – supported on WM9704M when DLM is set HSET = 1 indicates handset DAC/ADC is supported – ...
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... REGISTER 46H TO 48H – LINE1 AND 2 DAC/ADC LEVEL These registers are not supported in WM9704M, register 04h being used to control TX modem level. REGISTER 56H – MISCELLANEOUS MODEM AFE STATUS/CONTROL This read/write register defines the loop back modes available for the modem line and handset ADCs/DACs described in the Intel Specification ...
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... WM9704M The default value after cold or register reset for this register (0000h) defaults to all 0s specifying no wake-up event. Non-implemented GPIO pins always return 0s. REGISTER 54H – GPIO PIN STATUS The GPIO status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12 ...
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... Play Vendor ID code. The first character of that F0, the second character S7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In WM9704M the vendor ID is set to WML3 if MODE1 = 0, and WML4 if MODE1 = 1. ...
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... WM9704M SERIAL INTERFACE REGISTER MAP The following table shows the function and address of the various control bits that are loaded through the serial interface during write operations. Reg Name D15 D14 00h Reset X SE4 02h Master volume Mute X 04h Headphone vol. ...
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... AVSS NOTES: 1. Pins 27, 29 and 31 are internally connected recommended that AC-LINK capacitors only be connected to one of these pins C28 should be as close to WM9704M as possible. 3. AGND and DGND should be connected as close to WM9704M as possible. Figure 15 External Components Diagram WOLFSON MICROELECTRONICS LTD DVDD 1 ...
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... WM9704M RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT SUGGESTED REFERENCE VALUE 10nF C5 to C17 470nF C18 1 F C19 0.1 F C20 10 F C21 0.1 F C22 10 F C23 0.1 F C24 10 F C25 0.1 F C26 10 F C27 100nF C28 47nF C29 to C33 10 F C34 and C35 22pF XT 24.576 MHz Table 23 External Component Values RECOMMENDATIONS FOR 3 ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD -C- ccc C SEATING PLANE MAX 1.60 0.15 1.45 0.27 0.20 0. WM9704M DM003 Rev 3.2 January 2001 37 ...