isppac-powr604 Lattice Semiconductor Corp., isppac-powr604 Datasheet - Page 22

• Manufacturer Part Number: isppac-powr604
• Description: In-system Programmable Power Supply Sequencing Controller And Monitor
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-12. UES Register
PROGUES – This instruction will program the content of the UES Register into the UES E
device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs
into the SAFESTATE.
Notes:
In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in
which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E
using the corresponding erase instruction.
Application Example
The ispPAC-POWR604 device has six comparators to monitor various power supply levels. The comparators each
have a programmable trip point that is programmed by the user at design time. The output of the comparators feed
into the PLD logic array to drive the state machine logic or monitor logic. The outputs of comparators
COMP1...COMP6 are also routed to external pins to be monitored directly or can be used to drive additional control
logic if expansion is required. The comparator outputs are open-drain type output buffers and require a pull up
resistor to drive a logic high. All six comparators have hysteresis, the hysteresis is dependent on the voltage trip
point scale that is set, it ranges from 3.4mV for the 1.2V monitor supply range to 16.2mV for the 5.0V monitor sup-
ply range. The comparators can be set with a trip point from 1.03V to 5.72V, with 192 different values. The applica-
tion diagram shows a set-up that can monitor and control multiple power supplies. The digital outputs and inputs
are also used to interface with the board that is being powered up.
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
2-22
Bit
7
Bit
6
Bit
5
ispPAC-POWR604 Data Sheet
Bit
4
2
Bit
3
CMOS bits need to be erased
Bit
2
2
CMOS memory. The
Bit
1
Bit
0
TDO