ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 14

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

Interrupt Status and Control register ‘ISR’ (Offset 0x0C)
This register controls the assertion of interrupts from the User I/O pins (MIO[1:0]) as well as returning the internal status of the
interrupt sources.
Bits
7:5
4
3
2
1
0
Soft UART/Local Bus reset register ‘SRT’ (Offset 0x0D)
This register controls the soft reset passed to the UART and local bus reset. These reset lines are in addition to the soft reset
that may be produced by the host (bit[7] of the COR register in attribute memory space). Note that the local bus reset is used in
Local Bus mode only and not in Normal mode. Note these bits are not self - clearing.
Bits
7:2
1
0
5.4
5.4.1
PCMCIA/CF cards support pulse or level type interrupt signals to request interrupt service from the host system. The CIS of the
card specifies whether pulse, level or both types of interrupt can be generated. Once the host has read the CIS it is able to set
the LevlReq field in the Configuration Options Register (COR) to tell the card which type of interrupts should be generated.
The OXCF950 is capable of generating either type of interrupt. However, to reduce power consumption, the default CIS states
that only level type interrupts can be generated. A custom CIS can be constructed that specifies the card has the ability to
generate pulse type interrupts, if this is required, by using an external EEPROM.
The OXCF950 uses a programmable clock divider circuit to generate pulse type interrupts signals. The pulse that is generated is
one clock cycle (after division) in length. The divider circuit can be programmed by setting the contents of the Interrupt Pulse
OXFORD SEMICONDUCTOR LTD.
CF / PCMCIA Interrupt
Interrupt Generation
Description
Reserved
UART Interrupt status
This bit reflects the state of the internal UART interrupt
MIO[1] interrupt mask
When set to ‘1’ allows pin MIO[1] to assert an interrupt on the devices
IREQ# pin. The state of the MIO[1] signal that causes an interrupt is
dependent upon the polarity set by the register fields MIC[3:2].
MIO[0] interrupt mask
When set to ‘1’ allows pin MIO[0] to assert an interrupt on the devices
IREQ# pin. The state of the MIO[0] signal that causes an interrupt is
dependent upon the polarity set by the register fields MIC[1:0].
MIO1 Internal state
This bit reflects the state of the internal MIO[1]. The internal MIO[1] signal
reflects the non-inverted or inverted state of MIO[1] pin
MIO0 Internal state
This bit reflects the state of the internal MIO[0]. The internal MIO[0] signal
reflects the non-inverted or inverted state of MIO[0] pin
Description
Reserved
Active high soft reset for UART
Active high soft reset for Local Bus
Table 11: Soft UART / Local Bus Reset (LB reset used in Local Bus Mode only)
Table 10: Interrupt Status Register
OXCF950 DATA SHEET V1.1
EEPROM
EEPROM
W
W
W
W
-
-
-
-
-
Read/Write
Read/Write
PCMCIA
PCMCIA
R/W
R/W
R/W
R/W
R
R
R
R
R
Reset
Reset
Page 14
000000
000
0
0
0
X
X
0
0