ht82m73e Holtek Semiconductor Inc., ht82m73e Datasheet
ht82m73e
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ht82m73e Summary of contents
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... Low voltage reset function 20-pin SOP/SSOP, 28-pin SOP/SSOP package The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, Power Down and wake-up functions, Watchdog timer, motor driving, in- dustrial control, consumer products, subsystem control- lers, etc. 1 HT82M73E with error 5% DD May 14, 2008 ...
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... OSC1, OSC2 are connected to an external 6MHz or 27MHz crystal/resona- tor for the internal system clock. Negative power supply, ground Schmitt trigger reset input. Active low Positive power supply Battery input DC/DC LX switch +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 2 HT82M73E May 14, 2008 ...
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... WDT disable, LVR disable =0. =0. =0.9V 2 =0.9V 2 Test Conditions Min. V Conditions DD 3 WDTS HT82M73E Ta=25 C Typ. Max. Unit 3.3 V 4.5 V 1 Ta=25 C Typ. Max. ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 4 HT82M73E May 14, 2008 ...
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... Program Counter + 2 PC9 PC8 @ Program Counter 5 HT82M73E May 14, 2008 ...
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... ROM data as defined by TBLP and TBHP value. Otherwise, the ROM code option TBHP is dis- abled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. TBHP register bit0~bit2 when TBHP is enable 6 HT82M73E May 14, 2008 ...
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... The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] in- struction is executed. Table Location Bits Table Location 7 HT82M73E May 14, 2008 ...
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... Spe- cial Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H . Special Purpose Data Memory Structure 8 HT82M73E May 14, 2008 ...
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... IAR actually the address speci- fied by the Memory Pointer that the microcontroller will be directed to. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined increment memory pointer ; check if last memory location has been cleared 9 HT82M73E May 14, 2008 ...
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... OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Status Register 10 HT82M73E May 14, 2008 ...
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... Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain in a low-power state un- 11 HT82M73E May 14, 2008 ...
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... I/O pins. Programming Considerations Within the user program, one of the first things to con- sider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all 12 HT82M73E May 14, 2008 ...
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... The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFFFH the preload registers must first be cleared to 00H. It should be noted 13 HT82M73E May 14, 2008 ...
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... TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The timer-on bit, TON, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by Timer Mode Timing Chart 14 HT82M73E May 14, 2008 ...
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... In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logi- cal transitions on the PA2/TMR pin and not by the logic level. Event Counter Mode Timing Chart 15 HT82M73E May 14, 2008 ...
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... When the Timer/Event counter overflows, its corre- sponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. But the timer overflow can t wake-up if MCU Power down con- dition. 16 HT82M73E May 14, 2008 ...
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... EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. 17 HT82M73E May 14, 2008 ...
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... Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are al- tered by the interrupt service program, which may cor- rupt the desired control sequence, then the contents should be saved in advance. Interrupt Control Register Interrupt Structure 18 HT82M73E May 14, 2008 ...
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... RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initi- ated from this point. RES Reset Timing Chart 19 HT82M73E May 14, 2008 ...
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... To ensure reliable continuation of normal program execution after a reset occurs important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. 20 HT82M73E May 14, 2008 ...
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... C1 and C2 connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. In most applications, re- sistor R1 is not required, however for those applications Crystal/Ceramic Oscillator 21 HT82M73E RES Reset WDT Time-out (HALT) (HALT)* 000H 000H ...
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... If the system is woken interrupt, then two possi- ble situations may occur. The first is where the interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situa- 22 HT82M73E May 14, 2008 ...
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... RES pin, the second is using the watchdog software instruc- tions and the third is via a HALT instruction. There are only CLR WDT instruction to clear the Watch- dog Timer. Watchdog Timer Register Watchdog Timer 23 HT82M73E May 14, 2008 ...
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... Port A (12H Port B (14H Internal Register Port C Port (16H Note: The Internal Register data (PC5~PC7) will clear to zero after F/W read the register. Port D (18H Rev. 1.00 24 HT82M73E May 14, 2008 ...
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... Where LVD_Rd is the control signal of the DC/DC to check what is the battery voltage. In order to read 2.2 LVD signal correctly, the user must wait about 5 s after set LVD_Rd and then read the 2.2 LVD signal. For Battery-in is 2.2V, the output driving current has mini. 50mA 25 HT82M73E May 14, 2008 ...
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... SPI bus. SPI Registers There are two registers associated with the SPI Inter- face. These are the SBCR register which is the control register and the SBDR which is the data register. The SPI Block Diagram 26 HT82M73E May 14, 2008 ...
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... The CSEN bit in the SBCR register controls the overall function of the SPI interface. Setting this bit high, will en- able the SPI interface by allowing the SCS line to be ac- SPI Interface Control Register SPI Bus Timing 27 HT82M73E May 14, 2008 ...
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... WCOL bit can be disabled or enabled by a configuration option. Programming Considerations When the device is placed into the Power Down Mode note that data reception and transmission will continue. The TRF bit is used to generate an interrupt when the data has been transferred or received. 28 HT82M73E May 14, 2008 ...
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... MCU system clock selection: f SYS 14 WDT: enable or disable 15 TBHP function: enable or disable 16 DC-DC output voltage: 2.7V, 3.1V, 3.4V, 3.8V, 4.2V, 4.7V 17 LVR: enable or disable 18 LVD voltage: 2.2V or 2.0V 19 Lock page 0~3: unlock or 0H~3FFH 20 Lock page 4~6: unlock or 400H~6FFH 21 Lock page 7: unlock or 700H~7FFH Application Circuits Rev. 1.00 Options / SYS 29 HT82M73E May 14, 2008 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 30 HT82M73E May 14, 2008 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 31 HT82M73E Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 32 HT82M73E Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 33 HT82M73E May 14, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 34 HT82M73E May 14, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82M73E May 14, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 36 HT82M73E May 14, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 37 HT82M73E May 14, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 38 HT82M73E May 14, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82M73E May 14, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82M73E May 14, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 41 HT82M73E May 14, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 42 HT82M73E May 14, 2008 ...
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... Package Information 20-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 490 HT82M73E Max. 419 300 20 510 104 May 14, 2008 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 228 150 8 335 HT82M73E Max. 244 158 12 347 May 14, 2008 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 697 HT82M73E Max. 419 300 20 713 104 May 14, 2008 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 228 150 8 386 HT82M73E Max. 244 157 12 394 May 14, 2008 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 47 HT82M73E May 14, 2008 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 48 HT82M73E May 14, 2008 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm 24+0.3 0.1 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 Dimensions in mm 16+0.3 0.1 8 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 6.5 0.1 9 0.1 2.3 0.1 0.3 0.05 13.3 49 HT82M73E May 14, 2008 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 Dimensions 0.3 8 0.1 1.75 0.1 7.5 0.1 1.55+0.1 1.5+0.25 4 0.1 2 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.3 0.05 13.3 50 HT82M73E May 14, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 51 HT82M73E May 14, 2008 ...