lcmxo2-2000ze-1uwg49itr1 Lattice Semiconductor Corp., lcmxo2-2000ze-1uwg49itr1 Datasheet - Page 100

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lcmxo2-2000ze-1uwg49itr1

Manufacturer Part Number
lcmxo2-2000ze-1uwg49itr1
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet
www.latticesemi.com
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
August 2011
November 2010
January 2011
April 2011
May 2011
Date
Version
01.0
01.1
01.2
01.3
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Introduction
Section
Multiple
All
Initial release.
Included ultra-high I/O devices.
Recommended Operating Conditions table – Added footnote 3.
DC Electrical Characteristics table – Updated data for I
ical values updated.
Generic DDRX2 Outputs with Clock and Data Aligned at Pin
(GDDRX2_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for T
Generic DDRX4 Outputs with Clock and Data Aligned at Pin
(GDDRX4_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for T
Power-On-Reset Voltage Levels table - clarified note 3.
Clarified VCCIO related recommended operating conditions specifica-
tions.
Added power supply ramp rate requirements.
Added Power Supply Ramp Rates table.
Updated Programming/Erase Specifications table.
Removed references to V
Included number of 7:1 and 8:1 gearboxes (input and output) in the pin
information summary tables.
Removed references to V
Data sheet status changed from Advance to Preliminary.
Updated MachXO2 Family Selection Guide table.
Updated Supported Input Standards table.
Updated sysMEM Memory Primitives diagram.
Added differential SSTL and HSTL IO standards.
Updates following parameters: POR voltage levels, DC electrical char-
acteristics, static supply current for ZE/HE/HC devices, static power
consumption contribution of different components – ZE devices, pro-
gramming and erase Flash supply current.
Added VREF specifications to sysIO recommended operating condi-
tions.
Updating timing information based on characterization.
Added differential SSTL and HSTL IO standards.
Added Ordering Part Numbers for R1 devices, and devices in WLCSP
packages.
Added R1 device specifications.
Replaced “SED” with “SRAM CRC Error Detection” throughout the doc-
ument.
Added footnote 1 to Program Erase Specifications table.
Updated Pin Information Summary tables.
Signal name SO/SISPISO changed to SO/SPISO in the Signal Descrip-
tions table.
MachXO2 Family Data Sheet
7-1
DIA
DIA
and T
and T
CCP.
CCP.
Change Summary
DIB.
DIB.
Revision History
Preliminary Data Sheet DS1035
DS1035 Revision History
IL
, I
IH
. V
HYST
typ-

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