lc4064zc-75tn48i Lattice Semiconductor Corp., lc4064zc-75tn48i Datasheet - Page 36

• Manufacturer Part Number: lc4064zc-75tn48i
• Description: 1.8v In-system Programmable Ultra Low Power Plds
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispMACH 4000V/B/C Timing Adders
Optional Delay Adders
t
t
t
t
t
LVTTL_in
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
LVTTL_out
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
PCI_out
Slow Slew
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
INDIO
EXP
ORP
BLA
IOI
IOO
Input Adjusters
Output Adjusters
Adder
Type
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
INREG
MCELL
ROUTE
IN
GOE
IN
GOE
IN
GOE
IN
GOE
IN
GOE
BUF
BUF
BUF
BUF
BUF
BUF
Parameter
, t
, t
, t
, t
, t
, t
, t
, t
, t
, t
, t
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
Base
—
EN
EN
EN
EN
EN
EN
, t
, t
, t
, t
, t
DIS
DIS
DIS
DIS
DIS
,
,
,
,
,
Input register delay
Product term expander delay
Output routing pool delay
Additional block loading adder
Using LVTTL standard
Using LVCMOS 3.3 standard
Using LVCMOS 2.5 standard
Using LVCMOS 1.8 standard
Using PCI compatible input
Output configured as TTL buffer
Output configured as 3.3V buffer
Output configured as 2.5V buffer
Output configured as 1.8V buffer
Output configured as PCI compatible
buffer
Output configured for slow slew rate
Description
1
(Cont.)
36
ispMACH 4000V/B/C/Z Family Data Sheet
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.00
0.33
0.05
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-75
Max.
1.00
0.33
0.05
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-10
Max.
1.00
0.33
0.05
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Timing v.3.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns