gal20v8zd-15qp Lattice Semiconductor Corp., gal20v8zd-15qp Datasheet - Page 17

• Manufacturer Part Number: gal20v8zd-15qp
• Description: Zero Power E2cmos Pld Gal
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL20V8Z/ZD provides a reset signal to all
registers during power-up. All internal registers will have their Q
outputs set low after a specified time (
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
FEEDBACK/EXTERNAL
INTERNAL REGISTER
OUTPUT REGISTER
Q - OUTPUT
t
pr, 1 s MAX). As a result,
CLK
Vcc
Vcc
Vcc (min.)
Vcc
17
t
pr
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20V8Z/ZD.
First, the V
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.
Data
Output
Specifications GAL20V8Z
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
CC
wl
Tri-State
Control
t
su
rise must be monotonic. Second, the clock input
Feedback
Typical Output
Vcc
Feedback
(To Input Buffer)
GAL20V8ZD
t
pr time. As in
PIN
PIN