m52s32162a Elite Semiconductor Memory Technology Inc., m52s32162a Datasheet
m52s32162a
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m52s32162a Summary of contents
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... Elite Semiconductor Memory Technology Inc 16Bit x 2Banks Mobile Synchronous DRAM GENERAL DESCRIPTION The M52S32162A is 33,554,432 bits synchronous high data rate Dynamic RAM organized 1,048,576 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. M52S32162A LWE LDQM Column Decoder ...
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... OL ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 1MHz) ° Symbol C CLK ADD C OUT M52S32162A Value -1.0 ~ 3.6 -1.0 ~ 3.6 - 150 0.7 50 ° C ° Typ Max Unit 2.5 2.7 V 2.5 V +0.3 V DDQ 0 0 ...
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... CKE V (min), CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated, tCCD = tCCD (min) ≥ (min TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52S32162A ° Version -6 -7.5 100 80 0.3 ∞ = 0.2 =15ns 9 ∞ ∞ 1 =15ns 15 ∞ = ...
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... RCD t (min (min) 36 RAS t (max) RAS t (min (min) CDL t (min) RDL t (min) BDL t (min) CCD t (max) REF CAS latency=3 CAS latency=2 M52S32162A Unit / 0 DDQ ns V DDQ Version Unit -7 100 us 67 CLK 2 CLK ...
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... 2 1 SLZ - 6 t SHZ - 9 *All AC parameters are measured from half to half. -6 Symbol Unit Min Max - 5 SAC - 5 5 SHZ - 5.5 M52S32162A -7.5 -10 Max Min Max 9 1000 1000 Note Publication Date : Dec. 2008 Revision : 1 ...
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... Reserved Reserved Reserved Reserved Reserved M52S32162A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
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... ATCSR 0 0 Elite Semiconductor Memory Technology Inc TCSR PASR DS ATCSR M52S32162A A0 Address bus Extended Mode Register A2-0 Self Refresh Coverage 000 Full Array 001 1/2 of Full Array 010 1/4 of Full Array PASR 011 Reserved 100 Reserved 101 Reserved 110 ...
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... M52S32162A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
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... Entry Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) after the end of burst. RP M52S32162A DQM BA A10/AP RAS CAS ...
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... *Note M52S32162A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
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... Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M52S32162A Publication Date : Dec. 2008 Revision : 1.4 12/30 ...
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... Elite Semiconductor Memory Technology Inc M52S32162A Publication Date : Dec ...
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... Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Precharge (A- Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M52S32162A Cb0 Rb Db1 Db2 Db0 *Note4 Db0 Db2 Db1 *Note4 Row Active W r ite ...
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... HIGH Cb0 Qa0 Qb0 Qb1 Qb2 Qa1 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M52S32162A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...
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... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb0 QAa0 QAa1 QAa3 QAa2 Read (B-Bank) Row Active (B-Bank) M52S32162A CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb0 QBb2 QBb3 QAc0 QAc1 QBd0 ...
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... Elite Semiconductor Memory Technology Inc HIGH CBb RBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) (B-Bank) M52S32162A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) Publication Date : Dec ...
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... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note: 1.t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52S32162A Publication Date : Dec. 2008 Revision : 1.4 18/30 ...
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... Read with Auto Precharge Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M52S32162A ...
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... Elite Semiconductor Memory Technology Inc M52S32162A ...
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... *Note2 M52S32162A ...
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... Elite Semiconductor Memory Technology Inc M52S32162A Publication Date : Dec ...
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... Row Active (B-Bank) Read with Auto Precharge (A-Bank) M52S32162A * ...
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... Row Active Precharge Active Power-Down Power-down Exit Entry M52S32162A Read Active Power-down Exit Publication Date : Dec. 2008 Revision : 1 ...
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... Elite Semiconductor Memory Technology Inc *Note3 RAS M52S32162A ...
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... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52S32162A ...
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... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 L1 0.80 REF e 0.80 BSC 0° 10° Θ M52S32162A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- - Dimension in inch Min Norm Max 0.047 0.018 0.008 0.875 BSC 0.463 BSC ...
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... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 7.90 8.00 8.10 0.311 7.90 8.00 8.10 0.311 6.40 6.40 0.80 M52S32162A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date : Dec. 2008 Revision : 1.4 28/30 ...
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... Modify t (1.5ns => 2ns) and Move Revision History to the last 2. Add -6 speed grade 3. Modify the test condition of I 2008.12.29 4. Add the specification Modify the description about self refresh operation 6. Correct A9 bit of MRS M52S32162A Description spec (1ns => 1.5ns) SH ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52S32162A Publication Date : Dec. 2008 Revision : 1.4 30/30 ...