m52s32162a Elite Semiconductor Memory Technology Inc., m52s32162a Datasheet - Page 5

• Manufacturer Part Number: m52s32162a
• Description: 1m X 16bit X 2banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
AC OPERATING TEST CONDITIONS (V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Refresh period (4,096 rows)
Number of valid output data
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A maximum of eight consecutive AUTO REFRESH commands (with t
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6 μ s.)
Parameter
Parameter
DD
CAS latency=3
CAS latency=2
=2.5V
Symbol
t
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
CDL
RDL
BDL
CCD
REF
(min)
(min)
±
(min)
(min)
(min)
(max)
(min)
(max)
(min)
(min)
(min)
0.2V,T
A
= 0 C
°
12
18
18
36
60
-6
~ 70 C
0.9 x V
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
° )
Value
DDQ
Version
DDQ
DDQ
RFCmin
22.5
22.5
67.5
/ 0.2
-7.5
100
15
45
64
1
2
1
1
2
1
) can be posted to any given SDRAM, and
Revision : 1.4
Publication Date : Dec. 2008
-10
20
30
30
50
90
M52S32162A
Unit
CLK
CLK
CLK
CLK
ms
ns
ns
ns
ns
us
ns
ea
Unit
ns
V
V
V
5/30
Note
1
1
1
1
1
2
2
2
3
5
4