92hd89c Integrated Device Technology, 92hd89c Datasheet - Page 20

• Manufacturer Part Number: 92hd89c
• Description: Six Channel Hd Audio Codec
• Manufacturer: Integrated Device Technology

92HD89C
Six channel HD Audio codec optimized for low power
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
2.6.
2.7.
2.8.
2.9.
AFG D0
AFG D1
AFG D2
AFG D3
2.9.1.
Function
Port Presence Detect
state change
GPIO state change
The AFG D0 state is the active state for the device. All functions are active if their power state (if they
support power management at their node level) has been set to D0.
D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions
are active. The part will resume from theD1 to theD0 state within 1 mS.
The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers
and internal references remain active to keep port coupling caps charged and the system ready for a
quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state
within 2mS.
The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-
fiers and references are active but in a low power state to prevent pops. Resume times may be
longer than those from D2, but still less than 10mS to meet Intel low power goals. The default power
state for the Audio Function Group after power is applied is D3.
The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the
system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using
D3 whenever there are no active streams or other activity that requires the part to consume full
power. The system remains in S0 during this time. When a stream request or user activity requires
the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To
enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA ECR-15b /
Low Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and <
60mW when analog PC_Beep is enabled.
While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3
state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-
ior is as follows (see the ECR15b section for more information):
AFG D3cold
The D3cold power state is the lowest power state available that does not use vendor specific verbs.
While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus ECR 015b, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
HDA Bus active
Unsolicited Response
Unsolicited Response
20
HDA Bus stopped
Wake Event followed by
an unsolicited response
Wake Event followed by
an unsolicited response
V 0.91 08/09
92HD89C