zl30105 Zarlink Semiconductor, zl30105 Datasheet - Page 18

• Manufacturer Part Number: zl30105
• Description: Stratum 3 Redundant System Clock Synchronizer For T1/e1/sdh, Advanced Tca And H.110
• Manufacturer: Zarlink Semiconductor

where:
HMS=0: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode
was entered for 2 seconds, then the overall MTIE would be 20 ns. As the delay value for the TIE corrector circuit is
not updated, there is no 13 ns measurement error at this point. The phase can still drift for 20 ns when the PLL is in
Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the
phase is not accumulated.
3.4
The DPLL of the ZL30105 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as
shown in Figure 11. The data path from the phase detector to the limiter is tapped and routed to the lock detector
that provides a lock indication which is output at the LOCK pin.
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the limiter circuit.
Limiter - the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope compliant with the applicable standards. The phase
slope limit is dependent on the APP_SEL1:0 and SEC_MSTR pins and is listed in Table 2.
Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 1.8 Hz or 3.6 Hz, suitable to
provide Primary Master timing. When Secondary Master mode is selected (SEC_MSTR=1), the filter bandwidth is
set to 922 Hz. For stability reasons, the loop filter bandwidth for 2 kHz and 8 kHz reference inputs is limited to a
maximum of 14 Hz and 58 Hz respectively.
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-
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TIE Corrector Circuit
0.01 ppm is the accuracy of the Holdover mode
0 ns is the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode
13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode
when a new TIE corrector value is calculated
Digital Phase Lock Loop (DPLL)
Virtual Reference
REF2_SYNC
from
frame pulse
Detector
Phase
Figure 11 - DPLL Block Diagram
Limiter
Zarlink Semiconductor Inc.
ZL30105
Control State Machine
State Select from
18
Loop Filter
Controlled
Oscillator
Detector
Digitally
Lock
Feedback signal from
Frequency Select MUX
feedback frame pulse; F8o or F2ko
Frequency Synthesizer
LOCK
DPLL Reference to
Data Sheet