89hpes12n3a Integrated Device Technology, 89hpes12n3a Datasheet - Page 12

• Manufacturer Part Number: 89hpes12n3a
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES12N3A Data Sheet
T
MAX JITTER
T
ENTER TIME
T
1.
RX-EYE-MEDIUM TO
RX-IDLE-DET-DIFF-
RX-SKEW
Parameter
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
GPIO (synchronous output)
GPIO (asynchronous input)
Max time between jitter median & max deviation
Unexpected Idle Enter Detect Threshold Integration Time
Lane to lane input skew
GPIO
GPIO[7:0]
1.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
they are asynchronous.
Signal
1
Description
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Symbol
Tpw_13b
Table 11 GPIO AC Timing Characteristics
2
Reference
Edge
12 of 31
None
Tpw_13b
Min Max Unit
50
Min
—
1
ns
Typical
Reference
Diagram
Timing
1
Max
0.3
10
20
1
March 27, 2008
Units
ms
UI
ns