89hpes12n3a Integrated Device Technology, 89hpes12n3a Datasheet - Page 6

• Manufacturer Part Number: 89hpes12n3a
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES12N3A Data Sheet
JTAG_TRST_N
SWMODE[3:0]
JTAG_TDO
JTAG_TMS
JTAG_TCK
JTAG_TDI
V
RSTHALT
Signal
Signal
Signal
PERSTN
DD
V
V
DD
DD
CORE
PE
IO
Type
Type
Type
O
I
I
I
I
I
I
I
I
I
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES12N3A and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES12N3A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES12N3A switch
operating mode. These pins should be static and not change after the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Core V
I/O V
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
Table 5 System Pins (Part 2 of 2)
Table 7 Power and Ground Pins
DD
DD
. LVTTL I/O buffer power supply.
. Power supply for core logic.
Table 6 Test Pins
6 of 31
Name/Description
Name/Description
Name/Description
March 27, 2008