89hpes12n3a Integrated Device Technology, 89hpes12n3a Datasheet - Page 2

• Manufacturer Part Number: 89hpes12n3a
• Description: 12-lane, 3-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Product Description
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 12 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification revision 1.1.
SMBus Interface
provides full access to the configuration registers in the PES12N3A,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES12N3A to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
IDT 89HPES12N3A Data Sheet
Utilizing standard PCI Express interconnect, the PES12N3A
The PES12N3A contains two SMBus interfaces. The slave interface
Six pins make up each of the two SMBus interfaces. These pins
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– Utilizes advanced low-power design techniques to achieve low
– Supports PCI Power Management Interface specification
– Unused SerDes are disabled
– Ability to read and write any internal register via the SMBus
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Power Management
Testability and Debug Features
Eight General Purpose Input/Output Pins
Packaged in 19x19mm 324-ball BGA with 1mm ball spacing
Bit
Table 1 Master and Slave SMBus Address Assignment
• Supports device power management states: D0, D3
1
2
3
typical power consumption
(PCI-PM 1.1)
D3
cold
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
Address
SMBus
Slave
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
Address
Master
SMBus
hot
and
2 of 31
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES12N3A acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES12N3A registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES12N3A may be configured to operate in a split configuration as
shown in Figure 2(b).
two independent buses and thus multi-master arbitration is never
required. The PES12N3A supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
As shown in Figure 2, the master and slave SMBuses may be used
In the split configuration, the master and slave SMBuses operate as
Bit
Table 1 Master and Slave SMBus Address Assignment
4
5
6
7
SSMBADDR[5]
Address
SMBus
Slave
0
1
1
March 27, 2008
MSMBADDR[4]
Address
Master
SMBus
1
0
1