mh2080 Music Semiconductors, Inc., mh2080 Datasheet
mh2080
Related parts for mh2080
mh2080 Summary of contents
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... Cascadable for increased depth • Extensive set of control states for flexibility RAM containing • JTAG interface • RoHS compliant, Green HLA package Registers BCAM ( TCAM) JTAG Figure 1: Block Diagram HARRP MH2080 bus directly controls device /OE PA[3-0] AA[12-0] /MI /FI /MF /MM /FF TDO Rev. 1.1a ...
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... Word A contains the value to be stored and word M contains a mask value, with each position at which stored. The value to be written to bits 31-0 of the MH2080 is (A&M) and the value to be written to bits 63-32 of the MH2080 is (~A&M). A special instruction, CMPT DQ, performs the ternary comparison processing for IPv4 CIDR addresses ...
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Packet stream Figure 2: System Block Diagram (using controller RAM for associated data) Packet stream Figure 3: System Block Diagram (dedicated RAM for associated data) Rev. 1.1a RAM Controller HARRP RAM Controller Associated Data Result HARRP RAM 3 Control & ...
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... AA bus is active. /E (Chip Enable, Input) The /E input is the main chip enable and synchronizing control for the MH2080. When /E is HIGH, the chip is disabled and the DQ31-0 lines are held in their high-impedance state. The falling edge of /E registers the /W, /CS1, /CS2, /AV, /AC bus, DSC, and the /VB and DQ31-0 lines for a Write cycle ...
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... Comparison cycle. /RESET The /RESET input is used to reset the MH2080 to a known state. When the /RESET line is pulled LOW it causes the MH2080 to enter its reset state. After power is applied to ...
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... VDD, VSS (Positive Power Supply, Ground) These pins are the main power supply connections to the MH2080. VDD must be held at +3.3 Volts and ± 0.3 Volts relative to the VSS pin, which Volts, system reference potential, for correct operation of the device. Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined in the IEEE Standard Test Access Port and Boundary-scan Architecture IEEE Standard ...
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... FUNCTIONAL DESCRIPTION Data is read from and written to the MH2080 through the DQ31-0 lines. The Control bus, which is comprised of Chip Enable (/E), two Chip Selects (/CS1, /CS2), Write Enable (/W), Output Enable (/OE), Validity Bit Control (/VB), Address Valid (/AV), Data Segment Control (DSC), and the Address/Control inputs (AC bus) controls the MH2080. When the /AV line is LOW, the AC bus carries an address for random access into the Memory array ...
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... Write cycle. The daisy chains are persistent and are not conditioned by the /OE input. The MH2080 supports JTAG boundary-scan testing through the pins TCK, TMS, TDI, TDO, and /TRST, according to the IEEE 1149 Standard: Test Access Port and Boundary-scan Architecture ...
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... Software Control mode. If the instruction expects a Read cycle, and a Write cycle is executed, or vice versa, the function of the MH2080 is undefined. Such an error may lead to data loss, but will not damage the device physically. Rev. 1.1a A Read cycle with the /AV line HIGH will access the Status register, allowing results to be read back without loading a new instruction ...
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... DSC and AC5-0 lines are needed for full control of the device. In applications where a restricted number of control lines are available, or where speed is not critical, the MH2080 can be controlled in Software Control mode where the control states are loaded into the Instruction register through the DQ31-0 lines ...
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Active Address Interface PA:AA Bus The Active Address interface PA:AA bus carries the currently active address. The address source depends on the most recent control state that caused it to change. The possible address sources that are output on PA:AA ...
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PA:AA Bus and the Status Register The Status Register bits SR15-0 reflect the PA:AA bus under all conditions. The Status Register flags /MF, /MM, and /FF represent the local conditions within the device, and are not conditioned by the /MI ...
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... DS3-0 are the same as the Page Address value PA3-0 and the Device Select Enable bit, DS8, is set LOW. Setting DS8 HIGH prevents the Device Select register from enabling the MH2080 . All other bits are reserved and should be set LOW. See Table 6. Instruction Register ...
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... Device Select register. The conditions of the Device Select register, the /CS1 and /CS2 lines are sampled at the time of the falling edge of / particular MH2080 within a system, that CAM will be selected under the following conditions: (/CS1=LOW) OR (/CS2=LOW) OR ((DS8 = LOW) AND (DS3-0 = PA3-0)) ...
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... Note that the daisy chain resolves system-level prioritization combinatorially once initiated by /E going HIGH. Other cycles that do not affect the daisy chain or match results can take place in the MH2080 while the daisy chain is resolving, for example, WR CR, allowing some degree of pipelining. During a Write cycle, the Full flag will not change until /E goes HIGH during that cycle ...
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... Full Cascading The Full flag is set LOW in a particular MH2080 if the /FI line is LOW, and that device is full. During a Write cycle, the Full flag will not change until /E goes HIGH during that cycle. When the /FI line is HIGH, one or more locations are free in the higher-priority devices; therefore, when the /FI line is HIGH, whether or not that particular device is full, its /FF output will remain HIGH ...
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... This first write to the devices in the system must be through Software control. The following sequence writes a new value to the Configuration register under software control: 1. Write 006H to MH2080s (/AV = HIGH, DQ13 = LOW). The value 006H is the control state Write to Configuration register, WR FR, with no mask. /AV Rev ...
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... JTAG Function Instruction 000 EXTEST RESERVED 001 RESERVED 010 CLAMP 011 100 IDCODE INTEST 101 SAMPLE/PRELOAD 110 BYPASS 111 The MH2080 ID Code is: XAC08133H (X is the four-bit revision code) BSDL files are available; Semiconductors website or contact MUSIC Technical Support. check the MUSIC 18 Rev. 1.1a ...
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CONTROL STATE OVERVIEW Table 1: Control State Overview AC Bus /W = LOW xxx xxx 000 011 NOP xxx nnn 000 100 WR AR {MRnnn} xxx nnn 000 110 WR FR {MRnnn} xxx nnn 001 000 WR DS {MRnnn} xxx ...
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CONTROL STATE DESCRIPTIONS REGISTER READ/WRITE Control State: No Operation Mnemonic: NOP Binary Binary Op-Code: XXX XXX 000 011 /W: LOW /AV: HIGH PA:AA: n/c Scope: n/a Description: No operation. The device performs no operation during the cycle. No existing states ...
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Control State: Read Comparand Register Mnemonic: RDs CR Binary Op-Code: XXX XXX 000 101 /W: HIGH /AV: HIGH PA:AA: n/c Scope: S Description: Reads bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of the Comparand register to the DQ31-0 bus. ...
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Control State: Indirect Write at Address; Increment Address Register Mnemonic: WRs[AR]+{MRnnn} Binary Op-Code: XXX nnn 100 110 /W: LOW /AV: HIGH PA:AA: aaa Scope: AS Description: Writes data from the DQ31-0 bus to bits 31-0 (DSC LOW) or 63-32 (DSC ...
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Control State: Write at Next Free Address Mnemonic: WRs[NFA]{MRnnn} Binary Op-Code: XXX nnn 000 001 /W: LOW /AV: HIGH PA:AA: NFA Scope: NFD Description: Writes data from the DQ31-0 bus to bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of ...
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Control State: Move Data from Highest-Priority Matching Location to Comparand Register Mnemonic: MOV CR,[HPM]{MRnnn} Binary Op-Code: XXX nnn 001 110 /W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD Description: Moves data from the Highest-Priority Match address from the previous Comparison ...
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... DSC must be LOW. Control State: Reset Mnemonic: RST Binary Op-Code: XXX XXX 111 111 /W: LOW /AV: HIGH PA:AA: All 1s Scope: AS Description: Resets the MH2080. DSC must be LOW. ADDRESS REGISTER CONTROL Control State: Increment Address Register Mnemonic: INC AR Binary Op-Code: XXX XXX 100 100 ...
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Table 2: Reset Conditions Resource Memory Array Comparand Register Mask Registers 1-7 Address Register Instruction Register Next Free Address Register Device Select Register DS31-4 Reserved DS8 SELEN DS7-4 Reserved DS3-0 Device Select Status Register SR31 Reserved SR30-28 Flags SR27-26 Reserved ...
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Table 4: Status Register Bit Assignments Bit(s) Names 31 Reserved 30 /MF 29 /MM 28 /FF 27:26 Reserved 25:24 Active Address Type 23:20 Reserved 19:16 Page Address PA3-0 15:13 Reserved 12:0 Active Address AA12-0 Table 5: Next Free Register Bit ...
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ELECTRICAL Absolute Maximum Ratings Supply Voltage: -0.5 to 4.6 Volts Voltage on all other pins -0.5 to VDD +0.5 Volts (-2 Volts for 10 ns, measured at the 50% point) Temperature under bias -40° 85° C Storage Temperature ...
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AC Test Conditions Input Signal Transitions 0.0 Volts to 3.0 Volts Input Signal Rise Time < Input Signal Fall Time < Input Timing Reference Level 1.5 Volts Output Timing Reference Level 1.5 Volts Switching Test Figures ...
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SWITCHING CHARACTERISTICS No. Symbol Parameter 1a tELEL Chip Enable Cycle Time (Other Cycles) 1b tELEL Chip Enable Cycle Time (Compare Cycles) 2a tELEH Chip Enable LOW Pulse Width (Other Cycles) 2b tELEH Chip Enable LOW Pulse Width (Compare Cycles) 3 ...
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TIMING DIAGRAMS /E /CS1, or /CS2 /W /AV, DSC, AC Bus DQ31- 0, /VB /E /CS1 CS2, /W /AV, DSC, AC Bus DQ31- 0, /VB /FI 13 /FF Rev. 1. ...
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CS2 /AV, DSC, AC Bus 9 DQ31- 0, /VB /OE 21 PA:AA Bus 23 /MI 24 /FI /MF, /MM Figure 10: Compare Cycle /E 25 /RESET Figure 11: Reset Cycle /TRST TCLK TDI, ...
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PACKAGE TOP VIEW D Pin 1 indicator SIDE VIEW Min Symbol A 0. 0.15 e1 0.50 BSC e2 1.00 BSC Notes: 1. All dimensions are in millimeters. 2. ’e1’ and ’e2’ represent the basic land grid pitch. ...
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... ORDERING INFORMATION Part Number Organization MH2080 8192 x 64 http: //www.musicsemi.com Cycle Time Package 35 ns HLA email: info@musicsemi.com 34 Temperature 0–70° C Rev. 1.1a ...