mh2080 Music Semiconductors, Inc., mh2080 Datasheet - Page 21

• Manufacturer Part Number: mh2080
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S
Description: Reads bits 31-0 (DSC LOW) or 63-32 (DSC
HIGH) of the Comparand register to the DQ31-0 bus.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of Mask register
nnn. If nnn=000 then no data is written.
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S
Description: Reads bits 31-0 (DSC LOW) or 63-32 (DSC
HIGH) of Mask register nnn to the DQ31-0 bus. If
nnn=000 then the output is undefined.
MEMORY READ/WRITE
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: LOW PA:AA: aaa Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the address value present on the AC bus. The
write optionally can be masked by bits 31-0 (DSC LOW)
or 63-32 (DSC HIGH) of the mask register selected
through the Configuration register; when masking is
selected, only bits in the addressed location that
correspond to LOW values in the selected mask register
are updated. The validity of the location is set by the state
of the /VB input, /VB=LOW: Valid, /VB = HIGH: Empty.
This control state provides direct random access memory
writes. This control state, along with the Read cycle and
HIGH segment equivalents are the only ones that use
direct addressing. It is selected by the /AV line being
LOW. All other control states have the /AV line HIGH
whereby the AC bus carries a control code. This control
state is not available in software mode.
Rev. 1.1a
Read Comparand Register
RDs CR
XXX XXX 000 101
Write Mask Register
WRs MRnnn
XXX nnn 001 001
Read Mask Register
RDs MRnnn
XXX nnn 001 001
Direct Write at Address
WRs[aaa]
aaa
21
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: LOW PA:AA: aaa Scope: S
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the address
value present on the AC bus to the DQ31-0 bus. This
control state provides direct random access memory reads.
This control state, along with the Write cycle and HIGH
segment equivalents are the only ones that use direct
addressing. It is selected by the /AV line being LOW. All
other control states have the /AV line HIGH whereby the
AC bus carries a control code. During the Read cycle, the
/VB line carries the Validity Bit value of the addressed
location. This control state is not available in software
mode.
Control State:
Mnemonic:
Binary Op-Code:
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31-0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. This control state
provides indirect random access memory writes.
Control State:
Mnemonic:
Binary Op-Code:
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31-0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location.
RDs[AR]
Direct Read at Address
RDs[aaa]
aaa
Indirect Write at Address
WRs[AR]{MRnnn}
XXX nnn 000 000
Indirect Read at Address
XXX nnn 000 000