txc-03453b TranSwitch Corporation, txc-03453b Datasheet - Page 84

• Manufacturer Part Number: txc-03453b
• Description: Tl3m Device Triple Level Mapper
• Manufacturer: TranSwitch Corporation

September 2003
TL3M
TXC-03453B
PRELIMINARY TXC-03453B-MB, Ed. 3
PER CHANNEL TRANSMIT PATH OVERHEAD BYTES AND O-BIT DESCRIPTIONS
The nine Transmit Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, F3, K3, and N1 bytes. The POH
bytes may be individually transmitted from the POH interface, or from RAM locations written by the micropro-
cessor. When control bit POH2RAM is a 1, the POH interface byte selected for transmission is written into the
designated RAM location. For example, if EXC2 is set to 1, the transmit POH interface C2 byte is written into
the assigned RAM location, in addition to being transmitted. If EXC2 is set to 0, the transmitted byte is the
value written into the corresponding RAM location by the microprocessor. When a 0 is written into the
POH2RAM control bit, the capability of writing any of the selected POH interface bytes into their RAM locations
is disabled. However, individual bytes may still be transmitted from either the POH interface or the
microprocessor-written RAM location. This feature permits switching back and forth between a selected POH
interface byte or a RAM location for transmission, without having to re-initialize the RAM location. The following
table is a summary of this operation:
Address
XBC
XBD
XC5H, bit 4
POH2RAM
* e.g., nn = C2.
Bit
X
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TUG3NEW TUG-3 New Alarm - Three new pointer events
PLLLOC
Symbol
AISLOC
RPLOC
RFRST
TPLOC
ROVFL
XISTAT
L3ERR
TFRST
XC3H, bits 7-0
LOVFL
XPAIS
HINT
NEW
OOL
EXnn*
1
1
0
Hardware Interrupt Enable
Reserved: Must be set to zero when register is written.
New Alarm - NDF and 3x new pointer events (TUG-3 operation)
Receive FIFO Overflow/Underflow
Alarm Indication Signal Loss Of Clock
External STS-1 Alarm (ISTAn) signal detected as a 1 (if enabled)
External Path AIS (PAISn) signal detected as a 1 (if enabled)
Internal PRBS Test Analyzer bit error detected.
Leak FIFO Overflow/Underflow
Receive FIFO Reset Indication
Transmit FIFO Reset Indication
Desynchronizer Phase Lock Loop (PLL) Loss Of Clock
Transmit PLL loss of clock
Receive PLL loss of clock
PRBS Test Analyzer out of lock.
POH interface byte written into RAM, and also transmitted.
POH interface byte transmitted, but not written into RAM.
Microprocessor writes RAM value as required.
POH RAM value transmitted.
DATA SHEET
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Action for associated POH byte
Description