TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet
TXC-05802AIPQ
Specifications of TXC-05802AIPQ
Related parts for TXC-05802AIPQ
TXC-05802AIPQ Summary of contents
Page 1
... U.S. Patents No. 5,568,060; 5,901,146 U.S. and/or foreign patents issued or pending Copyright 1999 TranSwitch Corporation CUBIT-Pro and SARA-Lite are trademarks of TranSwitch Corporation TranSwitch, TXC, CellBus, CUBIT, SALI-25C and SARA are registered trademarks of TranSwitch Corporation TranSwitch Corporation • Tel: 203-929-8810 DESCRIPTION TM CUBIT- Pro is a single-chip solution for implementing cost effective ATM access systems ...
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... Loopback Cell Send, Receive and Relay ............................................................ 39 Memory Map Reset States .................................................................................. 40 Pin Diagram ............................................................................................................... 41 Pin Descriptions ......................................................................................................... 42 Absolute Maximum Ratings and Environmental Limitations ...................................... 48 Thermal Characteristics ............................................................................................. 48 Power Requirements ................................................................................................. 48 Input, Output and I/O Parameters ............................................................................. 49 Timing Characteristics ............................................................................................... 52 Memory Map .............................................................................................................. CUBIT- Pro TXC-05802 PAGE TXC-05802-MB Ed. 3, November 1999 ...
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... Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. LIST OF FIGURES Figure 1. CUBIT- Pro TXC-05802 Block Diagram .................................................. 5 Figure 2. CellBus Bus Structure ............................................................................. 6 Figure 3. CellBus Bus Frame Format ..................................................................... 7 CellBus Bus 16/32-User Modes - Frame Formats ...
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... Intel Microprocessor Write Cycle Timing .............................................. 71 Figure 52. Motorola Microprocessor Read Cycle Timing ...................................... 72 Figure 53. Motorola Microprocessor Write Cycle Timing ....................................... 73 Figure 54. Microprocessor Interrupt Timing ........................................................... 74 CUBIT- Pro TXC-05802 208-Pin Plastic Quad Flat Package ................ 83 Figure 55. Figure 56. CUBIT- Pro TXC-05802 and Related Product Applications in ATM Access Switching .................................................................... CUBIT- Pro ...
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... LCLOCK A(7-0) D(7-0) FRCABRCNG Figure 1. CUBIT- Pro TXC-05802 Block Diagram A block diagram of the CUBIT- Pro device is shown in Figure 1. Further information on device operation and the interfaces to external circuits is provided below in the following Operation section. On the cell inlet side of the CUBIT- Pro is circuitry associated with accepting cells from the line and passing them to the CellBus bus with an appropriate header ...
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... Bus Arbiter is included inside the CUBIT- Pro device. Any one CUBIT- Pro in a system may be selected to perform the bus arbitration function by setting its ENARB pin low. CUBIT- Pro CUBIT- Pro CUBIT- Pro Figure 2. CellBus Bus Structure - 6 - CUBIT- Pro TXC-05802 Data (32) Clock (2) Frame Acknowledge Congestion Indicator TXC-05802-MB Ed. 3, November 1999 ...
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... Byte 34 Byte 36 Byte 37 Byte 38 Byte 40 Byte 41 Byte 42 Byte 44 Byte 45 Byte 46 BIP-8 Unused Figure 3. CellBus Bus Frame Format - 7 - CUBIT- Pro TXC-05802 Byte 3 Byte 7 Byte 11 Byte 15 Byte 19 Byte 23 Byte 27 Byte 31 Byte 35 Byte 39 Byte 43 Byte Granted P E Terminal R N Number TXC-05802-MB Ed. 3, November 1999 ...
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... Point-to-Multipoint (Multicast): In multicast routing the cell arriving at the inlet port is sent to the subset of out- let ports that belong to the specific multicast session by means of selection in the receiving CUBIT-Pros. 32-User Mode Framing Pulse Request Users 1-16 Cell body Grant Users 17-32 Request Cell body Grant Request Users 1- CUBIT- Pro TXC-05802 Even Odd TXC-05802-MB Ed. 3, November 1999 ...
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... Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header CUBIT- Pro TXC-05802 0 Single Address_Data 0 Single Address_Control 0 Single Address_Loopback 0 Broadcast Address_Data 0 Broadcast Address_Control 0 Multicast Address_Data 0 Multicast Address_Control TXC-05802-MB Ed. 3, November 1999 ...
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... When control bit CRC4I (bit 4 in register 0EH) is set to 1 the internally generated CRC-4 is inverted for testing purposes. This bit has no effect on an exter- nally-supplied CRC-4. For operation in the CUBIT TXC-05801 mode with an externally-supplied CRC-4, bit CRC4EN should be set to 0, which is the default at power-up/reset. ...
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... Figure 6 for ATM Layer emulation. Similarly, Figure 7 shows the pin connections and byte counts for PHY Layer emulation. The ABRENA pin must be held high or left floating (it has internal pull-up) for proper UTOPIA mode operation. LINEDIV - 11 - CUBIT- Pro TXC-05802 LINEDIV LINEDIV TXC-05802-MB Ed. 3, November 1999 ...
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... Operating Mode: Outlet UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header Reserved Reserved Reserved Reserved TXC-05802-MB Ed. 3, November 1999 ...
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... Operating Mode: Outlet UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, 55 bytes: cell plus Tandem Routing Header Reserved Reserved Reserved Reserved TXC-05802-MB Ed. 3, November 1999 ...
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... Input GFC1 8 GFC0 COD(7-0) COSOC COCLAV COENB COCLK Outlet Microprocessor LMODE1 LMODE0 Operating Mode: Inlet Low High ALI-25: 53-byte cell - 14 - CUBIT- Pro TXC-05802 CellBus bus 32 CBD(31-0) CBRC CBWC CBF CBACK CBCONG Operating Mode: Outlet ALI-25: 53-byte cell TXC-05802-MB Ed. 3, November 1999 ...
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... CUBIT- Pro CellBus Bus 32 CBD(31-0) CBRC CBWC CBF CBACK CBCONG Operating Mode: Outlet Back-to-Back: 55 bytes, cell plus two bytes of Tandem Routing Header Back-to-Back: 53-byte cell Back-to-Back: 55 bytes, cell plus two bytes of Tandem Routing Header Back-to-Back: 53-byte cell TXC-05802-MB Ed. 3, November 1999 ...
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... Byte 45 Byte 46 Byte 46 Byte 47 Byte 47 55 Bytes 55 Bytes Inlet Outlet - 16 - CUBIT- Pro TXC-05802 GFC, VPI VPI, VCI 5 bytes, header VCI VCI, PT, CLP HEC Byte 0 Byte 1 Byte 2 48 bytes, data Byte 45 Byte 46 Byte 47 53 Bytes Inlet, Outlet Cell TXC-05802-MB Ed. 3, November 1999 ...
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... TXC-05802 CellBus bus 32 CBD(31-0) CBRC CBWC CBF CBACK CBCONG Operating Mode: Outlet 16-Bit: 28 words, cell plus one word of Tandem Routing Header 16-Bit: 27-word cell 16-Bit: 28 words, cell plus one word of Tandem Routing Header 16-Bit: 27-word cell Reserved TXC-05802-MB Ed. 3, November 1999 ...
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... CellBus Bus Routing Header Low Low Reserved - 18 - CUBIT- Pro TXC-05802 32 Operating Mode: Outlet 16-Bit: 28 words, cell plus one word of Tandem Routing Header 16-Bit: 27-word cell 16-Bit: 28 words, cell plus one word of Tandem Routing Header 16-Bit: 27-word cell Reserved TXC-05802-MB Ed. 3, November 1999 ...
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... VPI, VCI VCI, PT, CLP VCI VCI, PT, CLP Undefined HEC Undefined Byte 1 Byte 0 Byte 1 Byte 3 Byte 2 Byte 3 Byte 43 Byte 42 Byte 43 Byte 45 Byte 44 Byte 45 Byte 47 Byte 46 Byte 47 Low Byte Low Byte High Byte Cell from Outlet Queue GFCENA Bit TXC-05802-MB Ed. 3, November 1999 ...
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... Since the queue length now less than VBRLIMIT = 2, condition b) no longer exists and cell #6 carries no congestion marking (PT = X0X). VBRLIMIT = 2 Cell Cell Cell Cell # X0X X1X X1X X0X - 20 - CUBIT- Pro TXC-05802 Single Queue TXC-05802-MB Ed. 3, November 1999 ...
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... Cell Cell #4 #5 CBR CBR X1X X1X Cell VBRLIMIT = 2 #3 ABR X0X Cell Cell #7 #8 VBR VBR X1X X0X - 21 - CUBIT- Pro TXC-05802 CBR Cell Queue (Priority 2) Cell #6 CBR X1X VBR Cell Queue (Priority 3) ABR Cell Queue (Priority 4) TXC-05802-MB Ed. 3, November 1999 ...
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... Virtual Path Identifier (VPI) translation or VPI/VCI translation (where VCI is Virtual Circuit Identifier), and CellBus Bus Routing Header insertion, and Tandem Routing Header insertion, and F4 flow cell routing, and F5 flow cell routing CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... TRAM. The TRAM is organized into a block of VPI records and a block of VCI records, the contents of which are established by system control. Translation SRAM CS ADDR DATA WE OE Chip Select 8 18 Generation Logic TRA TRD TRWE TROE CUBIT- Pro - 23 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... UNI=1, TRHENA = (262144-(256*6))/(128*8) = 254 VCI Pages, if UNI=1, TRHENA = Min[(262144-(256*4))/(128*6), 256] = Min [340,256] = 256 VCI Pages. if VRPS[1,0]=1,1, VRP is 128. The maximum number of addressable pages is 256, even though, theoretically, 340 pages could fit in a SRAM of 256k bytes CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... VCI Page shown in Figure 19. VCI Page 0 Reserved VCs & Special Cells Figure 19. VCI Page 0 Organization (Bit OAMRMEN=1) If the device is required to operate in CUBIT TXC-05801 applications, then bit OAMRMEN must be set to 0, which is the power-up/reset default. VRPS[1,0] = 0,0 1535 VCI 255 Record ...
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... If the ignore bit is one (I= active (i.e., A=1 in the translation record) then incoming cells bearing this number are discarded, but not counted as misrouted cells. If control bit NOTIGN (bit 5 in register 0EH) is set to 1, then connections with I=1 will be treated CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... These bits are used to determine on which VPI/VCI OAM/RM cells are routed. The possible combinations are: C1,C0 = 0,0: the cell header is translated according to the values in the OAM/RM record (this value and OAMRMEN=0 should be selected for applications supporting CUBIT TXC-05801 functionality) C1,C0 = 0,1: for F4 flow this virtual path connection (VPC) OAM cells/RM-VPC cells are not routed according to the OAM/RM record ...
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... VCI Page Size records, allocated to this VPI (range from 16, where 0H=16). Relative address one contains the VCI Page Offset, which indicates where among the VCI pages the first utilized page starts. VP_Start_Addr = VP VP_Start_Addr = VP CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... VCI numbers to be inserted in the 3 VCI, 8 LSB cell, and the CellBus Bus Routing 2 VCI, 8 MSB Header to be used, are read from the 1 VPI, 8 LSB VCI translation record at the positions 1/0 VPI, 4 MSB indicated CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... E-bit in the translation record, and setting OAMRMEN bit (bit 1 in register 0EH For compatibility with CUBIT TXC-05801 applications, the bit OAMRMEN should be set to 0 (default). Both F4 and F5 flows are supported in the CUBIT- Pro . Depending on which flow is routed, two algorithms are used by the CUBIT- Pro (assuming OAMRMEN=1) ...
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... CellBus Bus Routing 2 VCI, 8 MSB Header to be used, are read from the 1 VPI, 8 LSB OAM translation record at the positions 1/0 VPI, 4 MSB indicated CUBIT- Pro TXC-05802 Route According to VP/VC Translation Route According Record VCI = 6? Yes Route According Page 0 TXC-05802-MB Ed. 3, November 1999 ...
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... Note: The M Field refers to the CellBus Bus Routing Header for Multicast Address cells (see Figure 5 this bit location enables multicast address 248 (M Field = F8H this bit location enables multicast address 0 (M Field = 00H) LSB Figure 25. Multicast Number Memory - 32 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... It is again the responsibility of system control to enable another arbiter. Upon switching from one arbiter to another, the receiving devices on the bus will automatically re-align to the new frame position within one CellBus bus frame. CUBIT- Pro CUBIT- Pro - 33 - CUBIT- Pro TXC-05802 +1.2V 0. Normally, one SS TXC-05802-MB Ed. 3, November 1999 ...
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... The control cell transmit buffer is loaded by the microprocessor with a cell to be sent to the CellBus bus. It can have any of the CellBus Bus Routing Header formats shown in Figure 5. Multicast and Broadcast cells in split-queue mode are sent to the VBR and CBR queues, respectively CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... Data Transfer Acknowledge DTACK is active low. When inactive, and pulled high by an external pull- up resistor, it requests microprocessor wait time. CUBIT- Pro Motorola Interface +5V +5V (ground). Connections are as shown in Figure 27. The SS (+5V). Connections are as shown in Figure 27. The DD5 - 35 - CUBIT- Pro TXC-05802 CUBIT- Pro PCLK SEL WR RD/WR IRQ DTACK MOTO TXC-05802-MB Ed. 3, November 1999 ...
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... In order to insure proper device initialization, after the loss of either the CellBus Bus Write Clock or the CellBus Bus Read Clock, an external hardware reset must be applied via the RESET pin. The hardware reset must be applied in the presence of all input clock signals. BIP-8 RESERVED - 36 - CUBIT- Pro TXC-05802 Bit 0 (LSB) CBLOF CBLORC CBLOWC TXC-05802-MB Ed. 3, November 1999 ...
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... More than CBRLEN (address 10H) cells try to accumulate in the CBR queue c. More than (89 minus CBRLEN) cells try to accumulate in the VBR queue d. More than 2 cells try to accumulate in the control queue. CTSENT NOGRT INSOC - 37 - CUBIT- Pro TXC-05802 Bit 0 (LSB) RESERVED OCOVF TXC-05802-MB Ed. 3, November 1999 ...
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... GFC=0, VPI 5 VPI, VCI VPI, VCI 6 VCI VCI 7 VCI, PT, CLP VCI, PT, CLP 8 Byte 0 Byte 0 9 Byte 1 Byte 1 10 Byte 2 Byte 2 53 Byte 45 Byte 45 54 Byte 46 Byte 46 55 Byte 47 Byte 47 Transmit Receive Control Cell Control Cell - 38 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... CUBIT- Pro devices. Care must be taken to ensure that no more than one CUBIT- Pro is trying to set up a loop- back into the same CUBIT- Pro , or mis-routing will ensue. address of CUBIT- Pro CellBus Bus Routing Header (single address control shown, see Figure LBADDRL (address 13H) LBADDRU (address 14H CUBIT- Pro TXC-05802 Memory Map of CUBIT- Pro B TXC-05802-MB Ed. 3, November 1999 ...
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... In order to insure proper device initialization, after the loss of either the CellBus Bus Write Clock or the CellBus Bus Read Clock, an external hardware reset must be applied via the RESET pin. The hardware reset must be applied in the presence of all input clock signals (1) ( CUBIT- Pro TXC-05802 Others A0-D7 (3) (3) ( TXC-05802-MB Ed. 3, November 1999 ...
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... SCAN1 205 TSTMODE- DEVHIZ- ENARB- Note: Due to space limitations, active low (inverted) or active-on-falling-edge signals are indicated by ’-’ at the end of their symbol (e.g., LMODE1- is equivalent to LMODE1). Figure 32. CUBIT- Pro TXC-05802 Pin Diagram CUBIT- Pro TXC-05802 Pin Diagram (Top View CUBIT- Pro ...
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... Connection of NC pins may impair performance or cause damage to the device. Some NC pins may be assigned functions in future upgrades of the device. Compatibility of the CUBIT- Pro TXC-05802 device in existing CUBIT TXC-05801 appli- cations may rely upon these pins having been left floating. ...
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... ALI-25 mode. TTL Cell Inlet Flag 4: EInt in ALI-25 mode. TTL Cell Inlet Start of Cell: Start-of-Cell indication for UTOPIA and 16-Bit modes. RDPrty parity in ALI-25 mode. (Note: Par- ity output of ALI-25 device is ignored by the CUBIT- Pro ). - 43 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... Force ABR Congestion: Active high signal to force a congestion indication for any ABR cells received. I TTLp Line Clock: Rising edge used for data transfer. This clock input is used for the cell Inlet/Outlet timing assuming that CLKS1,CLKS0=0,1 in register 0BH CUBIT- Pro TXC-05802 Name/Function TXC-05802-MB Ed. 3, November 1999 ...
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... VREF: Reference voltage for GTL receivers. Voltage VREF is approximately 2/3 V backplane termination voltage (nominally Vtt = +1.2V). The input connection to this pin is not part of the CellBus bus CUBIT- Pro TXC-05802 Name/Function and V power supplies. DD3 DD5 , where V is the tt tt TXC-05802-MB Ed. 3, November 1999 ...
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... TRD(7-0) are cell data inlet 8 LSB if ABRENA is enabled. TRD0 is LSB. High is logic 1. TTL 4 mA Translation RAM Output Enable: Active low output enable. TTL 4 mA Translation RAM Write Enable: Active low write enable CUBIT- Pro TXC-05802 Name/Function Name/Function TXC-05802-MB Ed. 3, November 1999 ...
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... Test Mode: Active low signal to enable device test by manufacturer. Tie Scan 1: Internal test function. Tie Scan 2: Internal test function. Tie Internal Test Pin: Leave floating Internal Test Mode Input: Tie CUBIT- Pro TXC-05802 Name/Function Name/Function . DD5 . DD5 TXC-05802-MB Ed. 3, November 1999 ...
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... Test Conditions o C/W 0 ft/min linear airflow Unit Test Conditions V mA See Notes 1 and 2 mW See Notes 1 and See Notes 1 and 2 mW See Notes 1 and See Note 2 mW See Note 2 mW See Notes 1 and ambient, and 40 MHz UTOPIA and TXC-05802-MB Ed. 3, November 1999 ...
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... CUBIT- Pro TXC-05802 Unit Test Conditions V 4.75 < V < 5. 4.75 < V < 5. Unit Test Conditions V 4.75 < V < 5. 4.75 < V < 5. Unit Test Conditions V 4.75 < V < 5. 4.75 < V < 5. DD5 pF Unit Test Conditions -4 4 TXC-05802-MB Ed. 3, November 1999 ...
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... CUBIT- Pro TXC-05802 Unit Test Conditions V V =4.75 6 this resistor is not provided the output DD5 Unit Test Conditions -6 6 Unit Test Conditions -8 8 Unit Test Conditions 4.75 < V < 5. 4.75 < V < TXC-05802-MB Ed. 3, November 1999 ...
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... V 0.4 V 8 CUBIT- Pro TXC-05802 Test Conditions 4.75 < V < 5.25 DD 4.75 < V < 4.75 -4 4.75 4 Test Conditions 4.75 < V < 5.25 DD 4.75 < V < 4.75 -6 4.75 6 Test Conditions 4.75 < V < 5.25 DD 4.75 < V < 4.75 -8 4.75 8 TXC-05802-MB Ed. 3, November 1999 ...
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... PCLK: CLKS[1:0] = 1,0 in UTOPIA/16-Bit (ATM Layer), Back-to-Back, and ALI-25 modes CICLK: PHYEN = Low only for UTOPIA/16-Bit (PHY Layer) +V )/2 for output signals. OL Input Clock Duty Cycle Min Typ Max Input Clock Frequency Min Typ Max - 52 - CUBIT- Pro TXC-05802 Unit Unit 42 MHz 42 MHz 42 MHz 42 MHz 42 MHz 42 MHz TXC-05802-MB Ed. 3, November 1999 ...
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... D(2b) t D(2c) t D(2d) t SU(1a) t SU(1b) t SU(1c) t SU(1d) t H(1a) t H(1b) t H(1c) t H(1d CUBIT- Pro TXC-05802 Data Data Valid Valid Min Typ Max 4.0 14 4.0 16 4.0 14 4.0 20 4.0 16 4.0 16 4.0 16 4.0 21 1.0 1.0 1.0 1.0 6.0 6.0 6.0 11 TXC-05802-MB Ed. 3, November 1999 Unit ...
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... Z(1a) t 4.0 Z(1b) t 4.0 Z(1c) t 4.0 Z(1d) t 4.0 D(2a) t 4.0 D(2b) t 4.0 D(2c) t 4.0 D(2d) t 4.0 D(3a) t 4.0 D(3b) t 4.0 D(3c) t 4.0 D(3d CUBIT- Pro TXC-05802 t Z(1a) t D(3a) t Z(1b) t D(3b) t Z(1c) t D(3c) t Z(1d) t D(3d) Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... SU(1) H(1) t D(1) t SU( P46 P47 t H(3) t H(2) t SU( P46 P47 t H(3) t H(2) Symbol Min t 10.5 SU(1) t 1.0 H(1) t 1.0 D(1) t 9.5 SU(2) t 1.0 H(2) t 10.0 SU(3) t 1.0 H( CUBIT- Pro TXC-05802 t D( Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... P43 P44 t H(3) t H(2) t SU( P43 P44 t H(3) t H(2) Symbol Min t 1.0 D(1) t 6.0 SU(1) t 0.0 H(1) t 6.0 SU(2) t 1.0 H(2) t 6.0 SU(3) t 1.0 H( CUBIT- Pro TXC-05802 P46 H1 H2 P45 P47 P45 P46 P47 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... COSOC delay after COCLK t H(1) t D(2) H2 P43 P44 P45 P46 P45 P46 H2 P43 P44 Symbol Min t 6.0 SU(1) t 1.0 H(1) t 1.0 D(1) t 1.0 D(2) t 1.0 D( CUBIT- Pro TXC-05802 P47 X X P47 H1 Typ Max Unit ns ns 6.0 ns 8.0 ns 7.0 ns TXC-05802-MB Ed. 3, November 1999 ...
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... COD(7-0) delay after COCLK COSOC delay after COCLK t H(1) t SU(1) t D(2) P45 X H2 P44 P46 H2 P44 P45 X P46 Symbol Min t 1.0 D(1) t 9.0 SU(1) t 1.0 H(1) t 1.0 D(2) t 1.0 D( CUBIT- Pro TXC-05802 P47 P47 H2 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... H2* H4 P45 P47 t H(4) t SU(3) H1* H3 P44 P46 t H(3) t H(2) Symbol Min t 9.5 SU(1) t 1.0 H(1) t 1.0 D(1) t 8.0 SU(2) t 1.0 H(2) t 8.0 SU(3) t 1.0 H(3) t 6.0 SU(4) t 1.0 H( CUBIT- Pro TXC-05802 t D( Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... D(1) t 6.0 SU(1) t 0.0 H(1) t 6.0 SU(2) t 1.0 H(2) t 6.0 SU(3) t 1.0 H(3) t 6.0 SU(4) t 1.0 H( CUBIT- Pro TXC-05802 P45 H2 H4 P43 P47 P44 H1 H2 P42 P46 P45 P43 P47 P42 P44 P46 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... P38 P40 Symbol Min t 6.0 SU(1) t 1.0 H(1) t 1.0 D(1) t 1.0 D(2) t 1.0 D(3) t 1.0 D( CUBIT- Pro TXC-05802 P45 P47 X X P44 P46 X X P45 P47 X H2 P44 P46 X H1 Typ Max Unit 6.0 7.0 8.0 7.0 TXC-05802-MB Ed. 3, November 1999 ...
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... P40 P42 X P44 t D(4) H4 P41 P43 X P45 t D(3) P42 X P44 H3 P40 Symbol Min t 1.0 D(1) t 6.0 SU(1) t 1.0 H(1) t 1.0 D(2) t 1.0 D(3) t 1.0 D( CUBIT- Pro TXC-05802 P47 X X P46 P47 H4 H1 P46 X H3 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... Min t 12 SU(1) t 0.0 H(1) t 1.0 D(1) t 8.0 SU(2) t 0.0 H(2) t 1.0 D(2) t 8.0 SU(3) t 0.0 H( SU(4) t 0.0 H( CUBIT- Pro TXC-05802 t H(1) t D(1) P31 P30 t D(2) t SU( H(3) SU(4) t H(4) FIFO Flush Sequence Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... COENB setup time before COCLK COENB hold time after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK D(1) t SU( Symbol Min t D( SU(1) t 0.0 H(1) t 1.0 D(2) t 1.0 D( CUBIT- Pro TXC-05802 53 t D(1) t H(1) P46 P47 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... CISOC setup time before CICLK CISOC hold time after CICLK SU(1) t D(1) t SU(2) P46 H(2) H(3) Symbol Min t 10 SU(1) t 0.0 H(1) t 1.0 D(1) t 9.0 SU(2) t 0.0 H(2) t 9.0 SU(3) t 0.0 H( CUBIT- Pro TXC-05802 t H(1) P47 Typ Max Unit 6.0 TXC-05802-MB Ed. 3, November 1999 ...
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... COENB setup time before COCLK COENB hold time after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK t D(1) t SU( D(3) Symbol Min t D( SU(1) t 0.0 H(1) t D( CUBIT- Pro TXC-05802 t D(1) t H(1) P46 P47 Typ Max Unit TXC-05802-MB Ed. 3, November 1999 ...
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... GFC(3-0) setup time before COCLK GFC(3-0) hold time after COCLK Figure 47. GFC Field Insertion Timing SU(1), SU( H(1), H(2) Symbol Min t 4.0 SU(1) t 0.0 H(1) Symbol Min t 0.0 SU(2) t 3.0 H( CUBIT- Pro TXC-05802 H5 P0 Typ Max Unit ns ns Typ Max Unit ns ns TXC-05802-MB Ed. 3, November 1999 ...
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... Please contact the TranSwitch Applications Engineering Department for additional information and support. HSpice is a registered trademark of Meta-Software, Inc. Figure 48. CellBus Bus Timing t SU(1) t H(1) t D(1) Symbol Min t 0.0 SU(1) t 6.0 H(1) t 6.0 D( CUBIT- Pro TXC-05802 Typ Max Unit ns ns See note ns TXC-05802-MB Ed. 3, November 1999 ...
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... Figure 49. CellBus Bus Frame Position, 16-User and 32-User Applications CBRC (Input) CBWC (Input) CBF* (U32 pin 16-user) DD5 CBF* (U32 pin 32-user) SS *Note: Output from the CUBIT- Pro that is selected to perform the bus arbitration function. Input to all other CUBIT-Pros on the CellBus bus CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... PW(1) Symbol Min Typ t 0.0 SU(1) t -10 D(1) t 1.0 F 0.0 t SU(2) t 0.0 H(1) t 0.0 H(2) t 0.0 D(2) t 0.0 PW(1) for proper operation. DD5 - 70 - CUBIT- Pro TXC-05802 H(1) t H(2) Max Unit Note 1 ns CellBus bus, LCLOCK or PCLK TXC-05802-MB Ed. 3, November 1999 ...
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... SU(3) t D(1) t PW(1) Symbol Min t 0.0 SU(2) t 5.0 H(1) t 0.0 H(2) t 0.0 SU(1) t 0.0 SU(3) t 0.0 D(1) t 0.0 PW(1) DD5 - 71 - CUBIT- Pro TXC-05802 t H(1) t H(2) Typ Max Unit Note 1 ns CellBus bus, LCLOCK or PCLK for proper operation. TXC-05802-MB Ed. 3, November 1999 ...
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... Translation RAM. t SU(2) t D(1) t D(2) Symbol Min t 0.0 SU(1) t 1.0 H(1) t D(1) t 5.0 H(2) t 0.0 SU(2) t 2*PCLK D( CUBIT- Pro TXC-05802 t H( H(2) Typ Max Unit ns 5 Note CellBus bus, LCLOCK or TXC-05802-MB Ed. 3, November 1999 ...
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... Translation RAM. t SU(2) t SU(1) t SU(3) t D(1) Symbol Min t 0.0 SU(2) t 0.0 SU(1) t 0.0 H(1) t 0.0 H(2) t 0.0 SU(3) t Note 1 D( CUBIT- Pro TXC-05802 t H( Typ Max Unit Note 2 10 CellBus bus, LCLOCK or PCLK TXC-05802-MB Ed. 3, November 1999 ...
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... Microprocessor Interrupt Generation Figure 54. Microprocessor Interrupt Timing PCLK (Input) Intel Interface: INT (Output) Motorola Interface: IRQ (Output) Parameter INT/IRQ delay after PCLK t D(1) Symbol Min Typ t 0.0 D( CUBIT- Pro TXC-05802 Max Unit 15 ns TXC-05802-MB Ed. 3, November 1999 ...
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... TIME(7-0) CBRLEN(6-0) CBRLIMIT(6-0) VBRLIMIT(6-0) LBADDRL(7-0) Reserved** TRAL(7-0) TRAU(7-0) TRADATA(7- CUBIT- Pro TXC-05802 Bit 2 Bit 1 Bit Reserved** CBLOF CBLORC CBLOWC RESET NOGRT Reserved** OCOVF INTEN2 Reserved** INTEN0 Reserved** CTRDY CRQSENT LINEDIV QM GFCENA IFECN MRCIN EBP OAMRMEN Reserved** LBADDRU(3-0) TXC-05802-MB Ed. 3, November 1999 ...
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... MRCHEAD0(7-0) MRCHEAD1(7-0) MRCHEAD2(7-0) MRCHEAD3(7-0) Reserved** Reserved** CRQ0(7-0) CRQ1(7-0) (61H) through CRQ50(7-0) (92H) CRQ51(7-0) Reserved** CTQ0(7-0) CTQ1(7-0) (A1H) through CTQ54(7-0) (D6H) CTQ55(7-0) Reserved** MCASTN00(7-0) MCASTN01(7-0) (E1H) through MCASTN1E(7-0) (FEH) MCASTN1F(7- CUBIT- Pro TXC-05802 Bit 2 Bit 1 Bit 0 CUBIT-ID(4-0) TRAMSB(1-0) TXC-05802-MB Ed. 3, November 1999 ...
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... Bit is set the CellBus bus write clock is not present for more than the equivalent of 32 PCLK cycles. Interrupt enabled for CTNAK Interrupt enabled for CTACK Reserved bits. Interrupt enabled for BIP- Interrupt enabled for CBLOF Interrupt enabled for CBLORC Interrupt enabled for CBLOWC CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... CellBus bus. Contains the address ID set at pins UA(4-0). These pin states are detected at power-up and if any of the UA(4-0) inputs change state. For example, CUBIT-ID is 1FH if the UA(4-0) pins are all high CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... ATM cell header (see Figure 47). Enable insertion of FECN The EFCI bit (middle bit of PT field) will be set =1 if the CBR or VBR FIFO length equals or exceeds the congestion limits, and IFECN = CUBIT- Pro TXC-05802 LINEDIV LINEDIV LINEDIV TXC-05802-MB Ed. 3, November 1999 ...
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... CIF1 and CIF3, respectively, when operating in UTOPIA or back-to-back modes. Also, EBP must be set order to tri-state CONGOUT when ONLINE=0. The default at power-up is EBP=0. cells. If set to 0, the CUBIT- Pro TXC-05802 uses CUBIT TXC-05801 OAM routing. The default at power-up is OAMRMEN=0. Reserved bit. Time-out counter preset value for bus access watchdog timer. If timer expires after a request is made, and before a grant is received, alarm bit NOGRT is set ...
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... LSB of the translation RAM address [pins TRA(7-0)]. Middle 8 bits of the translation RAM address [pins TRA(15-8)]. Data read from written into, the translation RAM at the address defined by pins TRA(17-0) [pins TRD(7-0)]. Reserved bits. 2 MSB of the translation RAM address [pins TRA(17-16 CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... Description Control cell receive buffer, 52 bytes ( 51). Control cell transmit buffer, 56 bytes ( 55). Description decimal, bits 7-0). Multicast session RX enable bits for channels 15-8, 23-16 247- 240 (relative addresses decimal, bits 7-0). 31 decimal, bits 7-0 CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... PIN #1 INDEX 208 1 SEE DETAIL “A” 0.60 0.20 DETAIL “A” Figure 55. CUBIT- Pro TXC-05802 208-Pin Plastic Quad Flat Package TRANSWITCH TXC-05802-AIPQ 25.50 REF (SQ) 28.00 0.10 (SQ) 30.60 0.25 (SQ) Notes: 1. All linear dimensions are shown in millimeters and are nominal unless otherwise indicated. ...
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... ORDERING INFORMATION Part Number: TXC-05802AIPQ RELATED PRODUCTS Figure 56 illustrates typical applications of the CUBIT- Pro CellBus Bus Switch device in a generic architecture for ATM access switching. The other TranSwitch devices included in this diagram are briefly described below: TXC-03003B, SOT-3 VLSI Device (STM-1, STS-3, STS-3c Overhead Terminator). This device performs all the functions for section, line and path overhead processing of STM-1, STS-3 or STS-3c signals, providing access to all overhead bytes ...
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... Figure 56. CUBIT- Pro TXC-05802 and Related Product Applications in ATM Access Switching SONET Ring SONET Cell Link T1 Cell Link ATM 25 Mbps Line Interface ATM Cell Interface CUBIT- Pro SOT-3 CDB SOT-3 SOT-3 CUBIT- Pro SOT-3 CDB SOT-3 SOT-3 CDB CUBIT- Pro QT1F- Plus ...
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... Publication Services of International Telecommunication Union (ITU) Telecommunication Standardization Sector (T) Place des Nations CH 1211 Geneve 20, Switzerland Tel: 41-22-730-5285 Fax: 41-22-730-5991 ATM Forum European Office 14 Place Marie - Jeanne Bassot Levallois Perret Cedex 92593 Paris France Tel Fax CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... Standardization Documents Order Desk 700 Robbins Avenue Building 4D Philadelphia, PA 19111-5094 Tel: 212-697-1187 Fax: 215-697-2978 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho - Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 Fax: 81-3-3432-1553 - 87 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... LIST OF DATA SHEET CHANGES This list of changes identifies areas within this updated CUBIT- Pro TXC-05802 Data Sheet that have signifi- cant differences relative to the previous, and now superseded, CUBIT- Pro TXC-05802 Data Sheet: Updated CUBIT- Pro TXC-05802 Data Sheet: Previous CUBIT- Pro TXC-05802 Data Sheet: The page numbers indicated below of this updated Data Sheet include changes relative to the previous Data Sheet ...
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... TranSwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - NOTES - - 89 - CUBIT- Pro TXC-05802 TXC-05802-MB Ed. 3, November 1999 ...
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... TranSwitch Corporation 3 Enterprise Drive Engines for Global Connectivity • • Shelton, CT 06484 USA Tel: 203-929-8810 - 90 - • • Fax: 203-926-9453 www.transwitch.com ...
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... Please fax this page to Mary Lombardo at (203) 926-9453 or fold, tape and mail it (see other side). ___________ Country: ______________ Y Y Windows Mac Y Y Sun Solaris __________ __________ - 91 - CUBIT- Pro TXC-05802 Y Y UNIX Other __________ TXC-05802-MB Ed. 3, November 1999 ...
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... TranSwitch product as it becomes avail- able. • TranSwitch Corporation 3 Enterprise Drive Engines for Global Connectivity (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Mary Lombardo 3 Enterprise Drive Shelton, CT 06484 U.S.A. • • ...