TXC-05802AIPQ Transwitch Corporation, TXC-05802AIPQ Datasheet - Page 38

• Manufacturer Part Number: TXC-05802AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-05802AIPQ

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / Rohs Status: Not Compliant

Control Queue Send and Receive
The formats of send (transmit) and receive control cells are shown in Figure 30. Reference to Figure 1 will be
helpful for understanding how cells are handled by the inlet and outlet control queues.
A cell can be sent from the microprocessor to the CellBus bus by using the control cell transmit buffer (Inlet
Control Queue in Figure 1). This ability allows the microprocessor to send any type of data, control or loopback
cell to any CUBIT- Pro on the CellBus bus. The microprocessor first writes a 56-byte transmit cell with the
format shown in Figure 30 to the control cell transmit buffer (Addresses A0H-D7H in the CUBIT- Pro memory
map). Then a 1 is written to control bit CTRDY (Address 0AH, Bit 1). The cell will be sent to the CellBus bus
after any pending data cells, and the CTSENT bit (Address 08H, Bit 3) will then be set to 1 and the CTRDY bit
will be reset to 0. Another such cell send sequence may be started after CTSENT has been received.
A four-cell FIFO buffer (Outlet Control Queue in Figure 1) is provided for reception of control cells from the Cell-
Bus bus, since control cells can arrive from several sources and may have to wait for the microprocessor to
accept them from the CUBIT- Pro . The FIFO output is the 52-byte memory segment CRQ(51-0) at Addresses
93H-60H. When this segment acquires a received control cell the CUBIT- Pro sets its interrupt bit CRQCAV to
1 (Address 08H, Bit 5). This bit may be enabled to cause an interrupt to the microprocessor (by setting inter-
rupt enable bit INTEN5 to 1 in Address 09H, Bit 5). When an interrupt or polling process causes the micropro-
cessor to read the interrupt event status register at Address 08H it will detect the CRQCAV indication that a
control cell is available for reading. It must then read CRQ(51-0) and set control bit CRQSENT to 1 upon com-
pletion (Address 0AH, Bit 0). This notifies the CUBIT- Pro to reset CRQCAV to 0 and place the next control cell
in CRQ(51-0), either immediately from the adjacent FIFO cell, if occupied, or whenever the next cell arrives in
the FIFO from the CellBus bus. The CUBIT- Pro resets CRQSENT to 0.
The CUBIT- Pro has a handshake mechanism whereby an interrupt can be generated indicating whether the
cell was received or not. Two bits are available, CTACK and CTNAK (bits 6 and 7 in register 05H) which are
set if the cell sent from the microprocessor interface was or was not accepted at the destination, respectively.
These interrupts are enabled by setting to 1 bits 6 and 7 in register 06H (INTENA6 and INTENA7).
Control cell transmission and reception may still be performed regardless of the state of control bit ONLINE
(Address 0CH, Bit 7).
Figure 30. Transmit and Receive Control Cell Formats
Byte #
10
53
54
55
0
1
2
3
4
5
6
7
8
9
CellBusBusRH MSB
CellBusBusRH LSB
TandemRH MSB
Control Cell
TandemRH LSB
VCI, PT, CLP
Transmit
GFC, VPI
VPI, VCI
Byte 45
Byte 46
Byte 47
Byte 2
Byte 0
Byte 1
VCI
- 38 -
Control Cell
VCI, PT, CLP
GFC=0, VPI
Receive
VPI, VCI
Byte 45
Byte 46
Byte 47
Byte 0
Byte 1
Byte 2
VCI
49
50
51
0
1
2
3
4
5
6
Ed. 3, November 1999
TXC-05802
CUBIT- Pro
TXC-05802-MB