am41pds3224d Meet Spansion Inc., am41pds3224d Datasheet - Page 4

• Manufacturer Part Number: am41pds3224d
• Description: 32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 4 Mbit 512 K ? 8-bit/256 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations. . . . . . . . . . . . . . . . 10
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Flash Command Definitions . . . . . . . . . . . . . . . . 22
May 13, 2002
Special Package Handling Instructions .................................... 7
Requirements for Reading Array Data ................................... 12
Read Mode ............................................................................. 12
Page Mode Read .................................................................... 12
Writing Commands/Command Sequences ............................ 12
Simultaneous Read/Write Operations with Zero Latency ....... 13
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 14
Autoselect Mode ..................................................................... 17
Sector/Sector Block Protection and Unprotection .................. 17
Write Protect (WP#) ................................................................ 18
Temporary Sector/Sector Block Unprotect ............................. 18
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Hardware Data Protection ...................................................... 21
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 22
Autoselect Command Sequence ............................................ 22
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23
Word Program Command Sequence ..................................... 23
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = V
Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = V
Random Read (Non-Page Mode Read) .............................. 12
Table 3. Page Word Mode ..............................................................12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 13
Table 4. Am29PDS322DT Top Boot Sector Addresses ..................14
Table 5. Am29PDS322DT Top Boot SecSi Sector Address ...........15
Table 6. Am29PDS322DB Bottom Boot Sector Addresses ............15
Am29PDS322DB Bottom Boot SecSi Sector Address.................... 17
Table 8. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................17
Table 9. Bottom Boot Sector/Sector Block Addresses for Protec-
tion/Unprotection .............................................................................18
Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 20
Factory Locked: SecSi Sector Programmed and Protected
at the Factory ...................................................................... 21
Low V
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Unlock Bypass Command Sequence .................................. 23
Figure 3. Unlock Bypass Algorithm ................................................. 24
Figure 4. Program Operation .......................................................... 24
CC
Write Inhibit ........................................................... 21
P R E L I M I N A R Y
Am41PDS3224D
SS
CC
11
10
Flash Write Operation Status . . . . . . . . . . . . . . . 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33
SRAM DC and Operating Characteristics . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Key To Switching Waveforms . . . . . . . . . . . . . . . 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50
Chip Erase Command Sequence ........................................... 24
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 25
DQ7: Data# Polling ................................................................. 28
RY/BY#: Ready/Busy# ............................................................ 29
DQ6: Toggle Bit I .................................................................... 29
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 ............................................... 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
CMOS Compatible .................................................................. 33
SRAM CE#s Timing ................................................................ 37
Hardware Reset (RESET#) .................................................... 40
Flash Erase and Program Operations .................................... 41
Temporary Sector/Sector Block Unprotect ............................. 46
Alternate CE#f Controlled Erase and Program Operations .... 48
Read Cycle ............................................................................. 50
Figure 5. Erase Operation.............................................................. 26
Table 10. Am29PDS322D Command Definitions ........................... 27
Figure 6. Data# Polling Algorithm .................................................. 28
Figure 7. Toggle Bit Algorithm........................................................ 29
Table 11. Write Operation Status ................................................... 31
Industrial (I) Devices ............................................................ 32
V
Figure 10. I
Sleep Currents) .............................................................................. 35
Figure 11. Typical I
Figure 12. Test Setup.................................................................... 36
Table 12. Test Specifications ......................................................... 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash ................................................................ 37
Figure 15. Conventional Read Operation Timings ......................... 38
Figure 16. Page Mode Read Timings ............................................ 39
Figure 17. Reset Timings ............................................................... 40
Figure 18. Program Operation Timings.......................................... 42
Figure 19. Accelerated Program Timing Diagram.......................... 42
Figure 20. Chip/Sector Erase Operation Timings .......................... 43
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 44
Figure 22. Data# Polling Timings (During Embedded Algorithms). 44
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 24. DQ2 vs. DQ6................................................................. 45
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram.............................................................................. 46
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram.............................................................................. 47
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings............................................................................... 49
Figure 28. SRAM Read Cycle—Address Controlled...................... 50
Figure 29. SRAM Read Cycle ........................................................ 51
CC
f/V
CC
s Supply Voltage ................................................... 32
CC1
Current vs. Time (Showing Active and Automatic
CC1
vs. Frequency ............................................ 35
3