k4t1g084qa-zce6 Samsung Semiconductor, Inc., k4t1g084qa-zce6 Datasheet - Page 3

• Manufacturer Part Number: k4t1g084qa-zce6
• Description: 1gb A-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

1G A-die DDR2 SDRAM
Key Features
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
Ordering Information
Note 1 : Speed bin is in order of CL-tRCD-tRP.
Note 2 : x4/x8 Package - including 8 dummy balls.
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
• Average Refresh Period 7.8us at lower than T
•
• All of Lead-free products are compliant for RoHS
Organization
pin, 333MHz f
strobe is an optional feature)
3.9us at 85qC < T
Package: 68ball FBGA - 256Mx4/128Mx8 , 84ball FBGA -
64Mx16
256Mx4
128Mx8
64Mx16
-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable
CAS Latency
tRCD(min)
tRC(min)
tRP(min)
CK
Speed
for 400Mb/sec/pin, 267MHz f
CK
for 667Mb/sec/pin
CASE
< 95 qC
K4T1G044QA-ZCE6
K4T1G084QA-ZCE6
K4T1G164QA-ZCE6
DDR2-667 5-5-5
DDR2-667 5-5-5
CK
15
15
54
5
for 533Mb/sec/
CASE
85qC,
Page 3 of 28
K4T1G044QA-ZCD5
K4T1G084QA-ZCD5
K4T1G164QA-ZCD5
DDR2-533 4-4-4
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8
banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x4) device receive 14/
11/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 68ball FBGAs(x4/x8) and in
84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
DDR2-533 4-4-4
15
15
55
4
K4T1G044QA-ZCCC
K4T1G084QA-ZCCC
K4T1G164QA-ZCCC
DDR2-400 3-3-3
DDR2-400 3-3-3
15
15
55
3
DDR2 SDRAM
Rev. 1.1 Aug. 2005
Package
68 FBGA
68 FBGA
84 FBGA
Units
tCK
ns
ns
ns