k4t56083qf Samsung Semiconductor, Inc., k4t56083qf Datasheet - Page 17

• Manufacturer Part Number: k4t56083qf
• Description: 256mb F-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

256Mb F-die DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DQ output access time
from CK/CK
DQS output access
time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold
time
DQ and DM input
setup time
Control & Address
input pulse width for
each input
DQ and DM input
pulse width for each
input
Data-out high-
impedance time from
CK/CK
DQS low-impedance
time from CK/CK
DQ low-impedance
time from CK/CK
DQS-DQ skew for
DQS and associated
DQ signals
DQ hold skew factor
DQ/DQS output hold
time from DQS
First DQS latching
transition to associated
clock edge
DQS input high pulse
width
DQS input low pulse
width
DQS falling edge to
CK setup time
DQS falling edge hold
time from CK
Parameter
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
min(tCL
, tCH)
2*tAC
tQHS
3000
tHP -
-0.25
min
-400
0.45
0.45
0.35
0.35
-450
175
100
0.35
min
min
0.6
tAC
0.2
0.2
x
DDR2-667
x
x
max
+400
8000
0.55
0.55
0.25
max
max
max
+450
tAC
tAC
tAC
240
340
x
x
x
x
x
x
x
x
x
x
min(tCL
Page 17 of 27
2* tAC
, tCH)
tQHS
3750
tHP -
-0.25
min
0.45
0.45
0.35
0.35
-500
-450
225
100
0.35
min
min
0.6
0.2
0.2
tAC
DDR2-533
x
x
x
max
+500
+450
8000
0.55
0.55
0.25
max
max
max
tAC
tAC
tAC
300
400
x
x
x
x
x
x
x
x
x
x
min(tCL
2* tAC
, tCH)
tQHS
5000
tHP -
-0.25
min
-600
-500
0.45
0.45
0.35
0.35
0.35
275
150
min
min
0.6
tAC
0.2
0.2
x
DDR2-400
x
x
max
+600
+500
0.55
0.55
8000
0.25
max
max
max
tAC
tAC
350
450
tAC
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Rev. 1.5 Feb. 2005
Notes
DDR2 SDRAM
15,16,
15,16,
20,21
17,20
17,21
24
27
27
22
21