k4h560838h Samsung Semiconductor, Inc., k4h560838h Datasheet - Page 12

• Manufacturer Part Number: k4h560838h
• Description: 256mb H-die Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

IDD7A : Operating current: Four bank operation
1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25°C; For DDR400: Vdd=2.6V,T=25°C
2. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
4. Timing patterns
14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A
IDD1 : Operating current: One bank operation
1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25°C; For DDR400: Vdd=2.6V,T=25°C
2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
3. Timing patterns
K4H560438H
K4H560838H
K4H561638H
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- A2(133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
- B3(166Mhz,CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with autoprecharge
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
- B0(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- A2 (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK
- B3(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC = 10*tCK, tRAS=7*tCK
- CC(200Mhz,CL = 3) : tCK = 5ns, CL = 3, BL = 4, tRCD = 3*tCK , tRC = 11*tCK, tRAS = 8*tCK
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
changing. lout = 0mA
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every transfer
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Read : A0 N N R0 N N P0 N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every transfer
Worst Case : Vdd = 2.7V, T= 10°C
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=DESELECT
Worst Case : Vdd = 2.7V, T= 10°C
Rev. 1.1 January 2006
DDR SDRAM