hys64t128020edl Qimonda, hys64t128020edl Datasheet - Page 16

• Manufacturer Part Number: hys64t128020edl
• Description: 200-pin Small-outlined Ddr2 Sdram Modules
• Manufacturer: Qimonda

1) For details and notes see the relevant Qimonda component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rev. 1.12, 2007-10
10312006-I253-V1V0
Parameter
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from
CK / CK
MRS command to ODT update delay
Mode register set command cycle
time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (8 banks) command
period
Read preamble
Read postamble
Active to active command period for
2KB page size products
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
Exit self-refresh to a non-read
command
Exit self-refresh to read command
Write command to DQS associated
clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
REFI
RFC
RP
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
DDR2–800
175
2 x
t
0
2
0
t
—
—
—
127.5
t
0.9
0.4
10
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
AC.MIN
HP
RP
RFC
–
+ 1 ×
t
AC.MIN
+10
t
QHS
t
CK
16
—
—
—
Max.
—
t
t
12
—
12
—
300
7.8
3.9
—
—
1.1
0.6
—
0.6
—
—
—
—
—
—
AC.MAX
AC.MAX
DDR2–667
200
2 x
t
0
2
0
t
—
—
—
127.5
t
0.9
0.4
10
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
Min.
AC.MIN
HP
RP
RFC
Small Outlined DDR2 SDRAM Modules
–
+ 1 ×
t
AC.MIN
+10
t
QHS
HYS64T128020EDL–[2.5/3S/3.7]–B
t
CK
Max.
—
t
t
12
—
12
—
340
7.8
3.9
—
—
1.1
0.6
—
—
—
0.6
—
—
—
—
—
—
—
AC.MAX
AC.MAX
Internet Data Sheet
Unit
ps
ps
ps
ns
nCK
ns
ps
ps
µs
µs
ns
ns
t
t
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Note
)6)7)8)
24)25)
9)22)
9)22)
35)
35)
26)
27)
28)29)
28)30)
31)
32)33)
32)34)
35)
35)
35)
35)36)
35)
2)3)5