mt9v125 aptina, mt9v125 Datasheet - Page 15

• Manufacturer Part Number: mt9v125
• Description: 1/4-inch System-on-a-chip Soc Vga Ntsc And Pal Cmos Digital Image Sensor
• Manufacturer: aptina

I/O Timing
Digital Output
Figure 10:
Table 5:
PDF: 09005aef829db8a0/Source: 09005aef829dbfdb
MT9V125_LDS_2.fm - Rev. A 4/07 EN
Signal
EXTCLK
PIXCLK
DATA[7:0]
FV/LV
Digital Output I/O Timing
T
Digital Output I/O Timing
Input
Output
Output
Output
A =
1
Ambient = 25°C; VDD = 2.5–3.1V
Notes:
FRAME_VALID
Parameter
t
t
t
f
t
t
t
t
t
t
t
t
t
extclk_low
extclk_period
extclkr_dout
extclkr_fvlv
extclk_high
extclk
pixclk_low
pixclk_high
pixclk_period
dout_su
dout_ho
fvlv_su
fvlv_ho
LINE_VALID
D
By default, the MT9V135 launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 10.
As an option, the polarity of the PIXCLK can be inverted from the default. This is
achieved by programming R155:1[9] to “0.”
1. PIXCLK may be inverted by programming register R155:1[9] = 0.
OUT
EXTCLK
PIXCLK
[7:0]
t extclkr_dout
t extclkr_fvlv
t pixclk_high
max +/- 100 ppm
Condition
MT9V125: 1/4-Inch VGA SOC Digital Image Sensor
t dout_su
t pixclk_low
15
t extclk_high
t dout_ho
t fvlv_su
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Minimum
36.7
17
17
14
14
14
14
14
14
–
8
8
t pixclk_period
Detailed Architecture Overview
t extclk_low
Typical
37.0
18.5
18.5
18.5
18.5
27
37
14
14
–
–
–
–
©2007 Micron Technology, Inc. All rights reserved.
t extclk_period
t fvlv_ho
Maximum
37.4
20
20
22
22
18
18
23
23
23
23
–
UNDEFINED
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns