mt9v125 aptina, mt9v125 Datasheet - Page 6

• Manufacturer Part Number: mt9v125
• Description: 1/4-inch System-on-a-chip Soc Vga Ntsc And Pal Cmos Digital Image Sensor
• Manufacturer: aptina

Ball Assignments
Figure 5:
Table 4:
PDF: 09005aef829db8a0/Source: 09005aef829dbfdb
MT9V125_LDS_2.fm - Rev. A 4/07 EN
Assignment
Ball
G1
G3
G4
G2
G5
H3
H5
F1
F2
Ball Descriptions
52-Ball iBGA Assignment
NTSC_PAL_SELECT
RESET_BAR
HORIZ_FLIP
PEDESTAL
STANDBY
EXTCLK
S
Name
RSVD
SCLK
ADDR
Figure 5 shows the location of the balls and their corresponding signals on the MT9V125.
The 12 balls in the middle of the package are unconnected.
G
H
A
D
B
C
E
F
RESET
_BAR
V
DIN4
DIN0
_CLK
DIN6
V
EXT
DIN
CLK
DD
1
DD
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
STANDBY
DIN2
DIN1
S
DIN7
DIN5
DIN3
S
DATA
CLK
2
D
S
D
SELECT
D
D
_PAL_
ADDR
NTSC
OUT
OUT
GND
GND
3
MT9V125: 1/4-Inch VGA SOC Digital Image Sensor
Two-wire serial interface device ID selection 1:0xBA, 0:0x90.
Must be attached to D
Two-wire serial interface clock.
Multifunctional signal to control device addressing, power-down,
and state functions (covering output enable function).
If “0” at reset: Default horizontal setting.
If “1” at reset: Flips the image readout format in the horizontal
direction.
If “0” at reset: Default NTSC mode.
If “1” at reset: Default PAL mode.
If “0” at reset: Does not add pedestal to composite video output.
If “1” at reset: Adds pedestal to composite video output.
Valid for NTSC only, pull LOW for PAL operation.
Master clock in sensor.
Active LOW: asynchronous reset.
4
5
(Ball Down)
Top View
D
D
ENABLE
RSVD
L
OUT
OUT
VDS_
4
6
2
3
PEDESTAL
D
D
HORIZ
_FLIP
OUT
OUT
5
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
VAAPIX
PIXCLK
VALID
A
LINE_
D
V
GND
GND
6
AA
GND
V
FRAME_
VALID
D
D
_LSB0
_LSB1
D
D
D
_NEG
DD
DAC
OUT
OUT
GND
OUT
7
OUT
. G4
PLL
6
Description
7
_POS
LVDS
_POS
V
DAC
LVDS
_NEG
_REF
D
V
DAC
V
DAC
DD
GND
DD
8
DD
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Ball Assignments