zicm0868p0 California Eastern Laboratories, zicm0868p0 Datasheet - Page 8

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zicm0868p0

Manufacturer Part Number
zicm0868p0
Description
868 / 900 Mhz System-on-chip Soc Based Modules
Manufacturer
California Eastern Laboratories
Datasheet
PIN SIGNALS I/O PORT CONFIGURATION
MeshConnect module has 56 edge I/O interfaces for connection to the user’s host board.
shows the layout of the 56 edge castellations.
MeshConnect I/O PIN ASSIGNMENTS
Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
P0.7/IREF Must be connected to SDN for SNAP firmware
RST/C2CK Debug Clock
P0.5/RXD Module's Internal UART RXD
P0.4/TXD Module's UART TXD
P2.7/C2D Debug Data
CNVSTR
GPIO0
GPIO2
Name
ANTA
P0.6/
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P0.3
P0.2
P0.1
P0.0
P2.6
P2.5
P2.4
P2.3
VCC
WP
NC
NC
NC
NC
NC
Available: Not used for any module functionality
Available: Not used for any module functionality
Available: Not used for any module functionality
Used as Chip Select for Memory on CEL Eval. Board
Write Protect Pin of Memory Chip on Module
Used as Chip Select for Memory IC on the CEL Module
Memory IC MISO signal pin
Must be connected to NIRQ for SNAP firmware
Memory IC Clock Signal
GPIO connected to Buzzer on CEL Eval Board
GPIO connected to Switch 3 on CEL Eval board
GPIO connected to LED3 on CEL Eval board
GPIO connected to Switch 2 on CEL Eval Board
Notes
MeshConnect™ Sub-G Module Series
The MeshConnect Module Dimensions
Page 8

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